Jinsu Lee

发表

A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture

Hoi-Jun Yoo, Jinmook Lee, Jinsu Lee, 2019, 2019 Symposium on VLSI Circuits.

Non-invasive optical control of endogenous Ca2+ channels in awake mice

Sangkyun Lee, Ho Min Kim, Nury Kim, 2020, Nature Communications.

The Hardware and Algorithm Co-Design for Energy-Efficient DNN Processor on Edge/Mobile Devices

Hoi-Jun Yoo, Dongjoo Shin, Jinmook Lee, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Low-Power Deep Neural Network Online Learning Processor for Real-Time Object Tracking Application

Hoi-Jun Yoo, Jinmook Lee, Jinsu Lee, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices

Hoi-Jun Yoo, Jinmook Lee, Sungpill Choi, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices

Hoi-Jun Yoo, Sungpill Choi, Jinsu Lee, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 0.55 V 1.1 mW Artificial Intelligence Processor With On-Chip PVT Compensation for Autonomous Mobile Robots

Youchang Kim, Hoi-Jun Yoo, Dongjoo Shin, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

An energy-efficient deep learning processor with heterogeneous multi-core architecture for convolutional neural networks and recurrent neural networks

Hoi-Jun Yoo, Dongjoo Shin, Jinmook Lee, 2017, 2017 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS).

14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks

Hoi-Jun Yoo, Dongjoo Shin, Jinmook Lee, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

An Energy-Efficient Sparse Deep-Neural-Network Learning Accelerator With Fine-Grained Mixed Precision of FP8–FP16

Hoi-Jun Yoo, Jinmook Lee, Jinsu Lee, 2019, IEEE Solid-State Circuits Letters.

An Overview of Energy-Efficient Hardware Accelerators for On-Device Deep-Neural-Network Training

H. Yoo, Jinsu Lee, 2021, IEEE Open Journal of the Solid-State Circuits Society.

7.7 LNPU: A 25.3TFLOPS/W Sparse Deep-Neural-Network Learning Processor with Fine-Grained Mixed Precision of FP8-FP16

Hoi-Jun Yoo, Jinmook Lee, Donghyeon Han, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

DNPU: An Energy-Efficient Deep-Learning Processor with Heterogeneous Multi-Core Architecture

Hoi-Jun Yoo, Dongjoo Shin, Jinmook Lee, 2018, IEEE Micro.

A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory

Hoi-Jun Yoo, Wooyoung Jo, Juhyoung Lee, 2021, 2021 Symposium on VLSI Circuits.

A 1.02-μW STT-MRAM-Based DNN ECG Arrhythmia Monitoring SoC With Leakage-Based Delay MAC Unit

Hongsik Jeong, Hoi-Jun Yoo, Changhyeon Kim, 2020, IEEE Solid-State Circuits Letters.

A 1.1 mW 32-thread artificial intelligence processor with 3-level transposition table and on-chip PVT compensation for autonomous mobile robots

Youchang Kim, Hoi-Jun Yoo, Dongjoo Shin, 2016, 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX).

DF-LNPU: A Pipelined Direct Feedback Alignment-Based Deep Neural Network Learning Processor for Fast Online Learning

Hoi-Jun Yoo, Donghyeon Han, Jinsu Lee, 2021, IEEE Journal of Solid-State Circuits.

OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer

Hoi-Jun Yoo, Wooyoung Jo, Juhyoung Lee, 2021, 2021 Symposium on VLSI Circuits.

A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices

Hoi-Jun Yoo, Jinsu Lee, Juhyoung Lee, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

14.3 A 0.55V 1.1mW artificial-intelligence processor with PVT compensation for micro robots

Youchang Kim, Hoi-Jun Yoo, Dongjoo Shin, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks

Juhyoung Lee, Jinsu Lee, Ji-Hoon Kim, 2021, IEEE Journal of Solid-State Circuits.

A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices

Hoi-Jun Yoo, Dongjoo Shin, Jinmook Lee, 2019, 2019 Symposium on VLSI Circuits.

SRNPU: An Energy-Efficient CNN-Based Super-Resolution Processor With Tile-Based Selective Super-Resolution in Mobile Devices

Hoi-Jun Yoo, Jinsu Lee, Juhyoung Lee, 2020, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

A 17.5-fJ/bit Energy-Efficient Analog SRAM for Mixed-Signal Processing

Youchang Kim, Hoi-Jun Yoo, Dongjoo Shin, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.