Katsuhiro Shimohigashi

发表

A High S/N Design on Multilevel Storage Dynamic Memory

Y. Nakagome, M. Aoki, Masashi Horiguchi, 1985 .

A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic

Kazuo Yano, Akihiro Shimizu, Katsuhiro Shimohigashi, 1990 .

Low voltage ULSI design: the lower, the better?

Katsuhiro Shimohigashi, K. Seki, 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.

A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logic

Kazuo Yano, Katsuhiro Shimohigashi, Takashi Nishida, 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

Semiconductor memory with multi-level storage structure.

Masashi Horiguchi, Yoshinobu Nakagome, Katsuhiro Shimohigashi, 1984 .

Low-Voltage ULSI Design (Special Section on the 1992 VLSI Circuits Symposium)

Katsuhiro Shimohigashi, Koichi Seki, 1993 .

A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM

Makoto Suzuki, Atsuo Watanabe, Katsuhiro Shimohigashi, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

A 65ns CMOS DRAM with a twisted driveline sense amplifier

Hitoshi Tanaka, Katsutaka Kimura, Katsuhiro Shimohigashi, 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Quasi-complementary BiCMOS for sub-3-V digital circuits

Takashi Nishida, Katsuhiro Shimohigashi, Mitsuru Hiraki, 1991 .

Low-voltage ULSI design

Katsuhiro Shimohigashi, Koichi Seki, 1993 .

A 65-ns 4-Mbit CMOS DRAM with a twisted driveline sense amplifier

Katsutaka Kimura, Katsuhiro Shimohigashi, Shinji Shimizu, 1987 .

4726021 Semiconductor memory having error correcting means

Masashi Horiguchi, Masakazu Aoki, Katsuhiro Shimohigashi, 1988 .

A 16-levels/cell dynamic memory

Y. Nakagome, Masakazu Aoki, Masashi Horiguchi, 1985 .

Special Issue on Low-Voltage, Low-Power Integrated Circuits

Katsuhiro Shimohigashi, 1995 .

TPM 8.3: A 23ns 4Mb CMOS SRAM with n.5t.tA Standby Current

Shojiro Asai, Shuji Ikeda, T. Masuhara, 1990 .

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register

Youji Idei, Katsuhiro Shimohigashi, Katsuyuki Sato, 1998 .

WPM 4.3: An 80ns 1Mb Flash Memory with On·Chip Erase/Erase-Veri fy Controller

S. Saeki, Takaaki Hagiwara, Takeshi Wada, 1990 .

Semiconductor Industry and It's R&D -Growth and Transformation-

Katsuhiro Shimohigashi, 2007 .

Characteristics of a Buried-Channel, Graded Drain with Punch-Through Stopper (BGP) MOS Device

Hideo Sunami, Katsuhiro Shimohigashi, Norikazu Hashimoto, 1981, 1981 Symposium on VLSI Technology. Digest of Technical Papers.

Centralized system level redundancy scheme for large-capacity memory systems

Toshio Sugano, Katsuhiro Shimohigashi, Toshio Sasaki, 1992 .

Recent Trends in High Density Memory Design PART 1 : Static RAM Design PART 2 : Dynamic RAM Design

Katsuhiro Shimohigashi, 1991 .

A 9 ns 1 Mb CMOS SRAM

S. Hanamura, Katsuhiro Shimohigashi, Toshiaki Yamanaka, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

Semiconductor integrated circuit, circuit programming system and circuit programming process same

Hiroo Masuda, Eiji Takeda, Yoshiaki Kamigaki, 1980 .

Redundancy Techniques for Dynamic RAMs

Katsuhiro Shimohigashi, Masamichi Ishihara, Shinji Shimizu, 1983 .

Fully symmetric cooled CMOS on

Kazuo Yano, Katsuhiro Shimohigashi, Toshiaki Masuhara, 1989 .

Redundancy Techniques for Dynamic RAMs

Katsuhiro Shimohigashi, Masamichi Ishihara, Shinji Shimizu, 1982 .

Alpha-particle-induced charge collection measurements for megabit DRAM cells

Kiyoo Itoh, Eiji Takeda, Toru Toyabe, 1989 .

0.1 mu m CMOS devices using low-impurity-channel transistors (LICT)

Shinji Okazaki, Tokuo Kure, Katsuhiro Shimohigashi, 1990, International Technical Digest on Electron Devices.

A 25 mu m/sup 2/, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity

Eiji Takeda, Koichiro Ishibashi, Katsuhiro Shimohigashi, 1988, Technical Digest., International Electron Devices Meeting.