Christophe Alias

发表

Research Program - Compilers, code optimization andhigh-level synthesis for software and hardware

Laure Gonnord, Matthieu Moy, Christophe Alias, 2017 .

TeMa : an Efficient Tool to find High-Performance Library Patterns in Source Code

Christophe Alias, 2005 .

Monoparametric Tiling of Polyhedral Programs

Guillaume Iooss, Sanjay Rajopadhye, Christophe Alias, 2021, International Journal of Parallel Programming.

Lawrence Rauchwerger, Silvius Rus, Christophe Alias, 2006, 2006 International Conference on Parallel Architectures and Compilation Techniques (PACT).

Automatic Generation of FPGA-Specific Pipelined Accelerators

Bogdan Pasca, Christophe Alias, Alexandru Plesco, 2011, ARC.

SToP : Scalable Termination analysis of (C) Programs (tool presentation)

Laure Gonnord, Guillaume Andrieu, Christophe Alias, 2012 .

Improving Communication Patterns in Polyhedral Process Networks pdf

Christophe Alias, 2018, ArXiv.

Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool

Alain Darte, Christophe Alias, Alexandru Plesco, 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs

Paul Feautrier, Laure Gonnord, Alain Darte, 2010, SAS.

Deciding Where to Call Performance Libraries

Denis Barthou, Christophe Alias, Denis Barthou, 2005, Euro-Par.

New Results - Memory Reuse and Modular Mappings

Alain Darte, Robert Schreiber, Christophe Alias, 2006 .

Fkcc: The Farkas Calculator

Christophe Alias, 2019, FM Workshops.

Estimation of Parallel Complexity with Rewriting Techniques

Laure Gonnord, Carsten Fuhs, Christophe Alias, 2016 .

High-Level Synthesis of Pipelined FSM from Loop Nests

Fabrice Rastello, Christophe Alias, Alexandru Plesco, 2016 .

FPGA-specific synthesis of loop-nests with pipelined computational cores

Bogdan Pasca, Christophe Alias, Alexandru Plesco, 2012, Microprocess. Microsystems.

Program Analysis and Source-Level Communication Optimizations for High-Level Synthesis

Alain Darte, Christophe Alias, Alexandru Plesco, 2011 .

Optimizing remote accesses for offloaded kernels: Application to high-level synthesis for FPGA

Alain Darte, Christophe Alias, Alexandru Plesco, 2012, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Algorithm recognition based on demand-driven data-.ow analysis

Denis Barthou, Christophe Alias, 2003, 10th Working Conference on Reverse Engineering, 2003. WCRE 2003. Proceedings..

A Compiler Algorithm to Guide Runtime Scheduling

Laure Gonnord, Samuel Thibault, Christophe Alias, 2019 .

Data-aware Process Networks

Christophe Alias, Alexandru Plesco, 2015 .

SToP : Scalable Termination analysis of (C) Programs

Laure Gonnord, Guillaume Andrieu, Christophe Alias, 2012 .

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA

Alain Darte, Christophe Alias, Alexandru Plesco, 2013, DATE 2013.

Kernel Offloading with Optimized Remote Accesses

Alain Darte, Christophe Alias, Alexandru Plesco, 2011 .

Scientific Foundations - Platform-Independent Code Transformations

Paul Feautrier, Alain Darte, Antoine Fraboulet, 2006 .

Method for automatic synthesis circuits, device and associated computer program

Christophe Alias, Alexandru Plesco, 2014 .

Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose

Alain Darte, Christophe Alias, Fabrice Baray, 2007, LCTES '07.

Software - Algorithms on Integer Lattices and Memory Reuse Module: Cl@k+Bee

Alain Darte, Christophe Alias, Fabrice Baray, 2006 .

Modular termination of C programs

Laure Gonnord, Guillaume Andrieu, Christophe Alias, 2012 .

Optimizing Affine Control With Semantic Factorizations

Christophe Alias, Alexandru Plesco, Christophe Alias, 2017, ACM Trans. Archit. Code Optim..

On the Recognition of Algorithm Templates

Denis Barthou, Christophe Alias, Denis Barthou, 2004, COCV@ETAPS.

Automatic Generation of FPGA-Specific Pipelined Accelerators LIP Research Report RR2010-37

Bogdan Pasca, Christophe Alias, Alexandru Plesco, 2010 .

Scientific Foundations - Program analysis and transformations for high-level synthesis

Paul Feautrier, Laure Gonnord, Alain Darte, 2010 .

FIFO Recovery by Depth-Partitioning is Complete on Data-aware Process Networks

Christophe Alias, 2018 .

Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors

Uday Bondhugula, Sriram Krishnamoorthy, J. Ramanujam, 2009, 2009 18th International Conference on Parallel Architectures and Compilation Techniques.

On Channel Restructuring for Complete FIFO Recovery

Christophe Alias, 2019 .

Contributions to Program Optimization and High-Level Synthesis. (Contributions à l'optimisation de programmes et à la synthèse de circuits haut-niveau)

Christophe Alias, 2019 .

Rank: A Tool to Check Program Termination and Computational Complexity

Paul Feautrier, Laure Gonnord, Alain Darte, 2013, 2013 IEEE Sixth International Conference on Software Testing, Verification and Validation Workshops.

Pipeline-aware Scheduling of Polyhedral Process Networks

Christophe Alias, Julien Rudeau, Christophe Alias, 2019 .

IMPACT 2011: First international workshop on polyhedral compilation techniques

Cédric Bastoul, Sanjay Rajopadhye, J. Ramanujam, 2011 .

On domain-specific languages reengineering

Denis Barthou, Christophe Alias, Denis Barthou, 2005, GPCE'05.

Optimisation de programmes par reconnaissance de templates. (Program Optimization by Template Recognition and Replacement)

Christophe Alias, 2005 .

Lattice-Based Array Contraction: From Theory to Practice

Alain Darte, Christophe Alias, Fabrice Baray, 2007 .

New Results - Data-aware Process Networks

Christophe Alias, Alexandru Plesco, 2015 .