G. Masera

M. Casu, M. Zamboni, G. Masera, 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders

A. Baghdadi, G. Masera, C. Condo, 2014, Circuits, Systems, and Signal Processing.

Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders

Amer Baghdadi, Guido Masera, Carlo Condo, 2014, Circuits, Systems, and Signal Processing.

On chip interconnects for multiprocessor turbo decoding architectures

Amer Baghdadi, Guido Masera, Maurizio Martina, 2011, Microprocess. Microsystems.

Low-Complexity Reconfigurable DCT-V Architecture

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis †

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2020, Sensors.

Adaptive Approximated DCT Architectures for HEVC

Guido Masera, Maurizio Martina, G. Masera, 2017, IEEE Transactions on Circuits and Systems for Video Technology.

Analysis of HEVC transform throughput requirements for hardware implementations

Guido Masera, Enrico Masala, Maurizio Martina, 2017, Signal Process. Image Commun..

Approximate Arai DCT Architecture for HEVC

Guido Masera, Maurizio Martina, Giovanni Renda, 2017, 2017 New Generation of CAS (NGCAS).

Comparison between HEVC and Thor based on objective and subjective assessments

Guido Masera, Maurizio Martina, Paola Sunna, 2016, 2016 International Conference on Systems, Signals and Image Processing (IWSSIP).

Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding

Guido Masera, Enrico Masala, Maurizio Martina, 2015, 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP).

Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation by Using a Graphics Processing Unit and Dedicated Hardware

Enrico Magli, Guido Masera, Maurizio Martina, 2015, IEEE Transactions on Circuits and Systems for Video Technology.

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2015, Integr..

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2014, 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing.

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation

Frank Kienle, Amer Baghdadi, Christophe Moy, 2012, VLSI Design.

Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm

Amer Baghdadi, Guido Masera, Michel Jézéquel, 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

A high accuracy-low complexity model for CMOS delays

Massimo Ruo Roch, Gianluca Piccinini, Mario R. Casu, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

FPGA implementation of time-frequency analysis algorithms for laser welding monitoring

Guido Masera, Maurizio Martina, Fabrizio Vacca, 2009, Microprocess. Microsystems.

A new performance evaluation metric for sub-optimal iterative decoders

Guido Masera, Ashwani Singh, Emmanuel Boutillon, 2009, IEEE Communications Letters.

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead

Muhammad Shafique, Guido Masera, Alberto Marchisio, 2020, IEEE Access.

An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks

Muhammad Shafique, Guido Masera, Maurizio Martina, 2020, Future Internet.

Coded 16-PSK: Effects of Imperfect Carrier Recovery and Resolution of Phase Ambiguities

Gabriella Olmo, Guido Masera, Sergio Benedetto, 1987 .

Odd type DCT/DST for video coding: Relationships and low-complexity implementations

Guido Masera, Maurizio Martina, Maurizio Masera, 2017, 2017 IEEE International Workshop on Signal Processing Systems (SiPS).

Quantum Dot Cellular Automata Check Node Implementation for LDPC Decoders

Massimo Ruo Roch, Mariagrazia Graziano, Muhammad Awais, 2013, IEEE Transactions on Nanotechnology.

An LDPC Decoder Architecture for Wireless Sensor Network Applications

Guido Masera, Maurizio Martina, Andrea Dario Giancarlo Biroli, 2012, Sensors.

Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World

Massimo Ruo Roch, Guido Masera, Maurizio Martina, 2019, Future Internet.

CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor

Guido Masera, Maurizio Martina, Alberto Marchisio, 2021, 2021 International Joint Conference on Neural Networks (IJCNN).

Unequal Error Protection of Memories in LDPC Decoders

Guido Masera, Paolo Montuschi, Carlo Condo, 2015, IEEE Transactions on Computers.

Performance evaluation of a VLSI associative unifier in a WAM based environment

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 1991 .

R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors

Guido Masera, Maurizio Martina, Alberto Marchisio, 2021, 2021 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS).

DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks

Guido Masera, Maurizio Martina, Alberto Marchisio, 2021, 2021 International Joint Conference on Neural Networks (IJCNN).

Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator

Paola Bisaglia, Guido Masera, Igor S. Stievano, 2016, IEEE Transactions on Industrial Electronics.

Look-ahead sphere decoding: algorithm and VLSI architecture

Micaela Troglia Gamba, Guido Masera, G. Masera, 2011, IET Commun..

Look-Ahead Sphere Decoding: Algorithm and performance evaluation

Micaela Troglia Gamba, Guido Masera, G. Masera, 2009, 2009 6th International Symposium on Wireless Communication Systems.

Unified turbo/LDPC code decoder architecture for deep-space communications

Guido Masera, Carlo Condo, G. Masera, 2014, IEEE Transactions on Aerospace and Electronic Systems.

Accelerating channel codes simulations with a mixed hardware-software system architecture

A. Dassatti, G. Masera, F. Besuzzi, 2006, 2006 6th International Workshop on System on Chip for Real Time Applications.

Real-time implementation of fast discriminative scale space tracking algorithm

Guido Masera, Maurizio Martina, Muhammad Awais, 2021, Journal of Real-Time Image Processing.

Multiplierless, Folded 9/7– 5/3 Wavelet VLSI Architecture

Guido Masera, Maurizio Martina, G. Masera, 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

An application specific instruction set processor based implementation for signal detection in multiple antenna systems

Guido Masera, Maurizio Martina, M. Tamagnone, 2012, Microprocess. Microsystems.

Primo: Reconfigurable Platform for Wideband WirelessCommunications

Gabriella Olmo, Guido Masera, Sergio Benedetto, 2004 .

FFT processor: a case study in ASIP development

Gerd Ascheid, Heinrich Meyr, Guido Masera, 2005 .

Analysis on parallel implementations of fixed-complexity sphere decoder

G. Masera, Bin Wu, 2013, Science China Information Sciences.

PRIMO: Reconfigurable Platforms fro Wideband Wireless Communications

Gabriella Olmo, Guido Masera, Sergio Benedetto, 2004 .

Coupled electro-thermal modeling and optimization of clock networks

Gianluca Piccinini, Mariagrazia Graziano, Mario R. Casu, 2003, Microelectron. J..

Clock Distribution Network Optimization under Self-Heating and Timing Constraints

Gianluca Piccinini, Mariagrazia Graziano, Mario R. Casu, 2002, PATMOS.

Proxima: Prolog Execution Machine

M. Ruo Roch, G. Masera, G. Piccinini, 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

Cell library development using multi-objective function optimization

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

Multiplierless Mumford and Shah Functional Implementation

Guido Masera, Maurizio Martina, G. Masera, 2011, Circuits Syst. Signal Process..

Mumford and Shah functional: VLSI analysis and implementation

Guido Masera, Maurizio Martina, G. Masera, 2006, IEEE Transactions on Pattern Analysis and Machine Intelligence.

Low-Complexity, Efficient 9/7 Wavelet Filters VLSI Implementation

Guido Masera, Maurizio Martina, G. Masera, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives

G. Masera, M. Martina, Alessandra Dolmeta, 2023, Prime.

Implementation and integration of Keccak accelerator on RISC-V for CRYSTALS-Kyber

G. Masera, M. Martina, Alessandra Dolmeta, 2023, ACM International Conference on Computing Frontiers.

SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers

G. Masera, M. Shafique, Alberto Marchisio, 2023, 2023 International Joint Conference on Neural Networks (IJCNN).

An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding

Guido Masera, Maurizio Martina, Maurizio Masera, 2020, IEEE Transactions on Circuits and Systems for Video Technology.

A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection

Frank Kienle, Guido Masera, Bin Wu, 2012, VLSI Design.

LDPC check node implementation using reversible logic

Muhammad Awais, Guido Masera, Ashfaq Ahmed, 2019, IET Circuits Devices Syst..

Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding

Amer Baghdadi, Guido Masera, Carlo Condo, 2014, IET Commun..

A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study

Amer Baghdadi, Guido Masera, Carlo Condo, 2013, 2013 Euromicro Conference on Digital System Design.

VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture

Guido Masera, Maurizio Martina, Carlo Condo, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

Improving Network-on-Chip-based Turbo Decoder Architectures

G. Masera, M. Martina, 2013, Journal of Signal Processing Systems.

A joint communication and application simulator for NoC-based SoCs pdf

Amer Baghdadi, Guido Masera, Carlo Condo, 2013, ArXiv.

Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder

Guido Masera, Bin Wu, G. Masera, 2012, IET Commun..

On Practical Implementation and Generalizations of $ \max^{\ast}$ Operator for Turbo and LDPC Decoders

Guido Masera, P. Takis Mathiopoulos, Maurizio Martina, 2012, IEEE Transactions on Instrumentation and Measurement.

A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods

Guido Masera, Carlo Condo, G. Masera, 2011, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP).

A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder

Guido Masera, Ashwani Singh, Emmanuel Boutillon, 2011, 2011 14th Euromicro Conference on Digital System Design.

Scalable, High Throughput LDPC Decoder for WiMAX (802.16e) Applications

Guido Masera, Ashwani Singh, Muhammad Awais, 2011, ACC.

A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture pdf

Guido Masera, Carlo Condo, G. Masera, 2011, ArXiv.

Improving Network-on-Chip-based Turbo Decoder Architectures

Guido Masera, Maurizio Martina, G. Masera, 2011, J. Signal Process. Syst..

ALOE-Based Flexible LDPC Decoder

Guido Masera, Vuk Marojevic, Antoni Gelonch, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

VLSI Architectures for WIMAX Channel Decoders pdf

Guido Masera, Maurizio Martina, G. Masera, 2009, ArXiv.

Vlsi Implementation of WiMAX Convolutional Turbo Code Encoder and Decoder

Guido Masera, Maurizio Martina, Mario Nicola, 2009, J. Circuits Syst. Comput..

Design of a VLSI Decoder for Partially Structured LDPC Codes

Guido Masera, Libero Dinoi, Fabrizio Vacca, 2008, Int. J. Digit. Multim. Broadcast..

Reconfigurable Architecture for LDPC and Turbo Decoding: A NoC Case Study

E. Boutillon, G. Masera, A. Singh, 2008, 2008 IEEE 10th International Symposium on Spread Spectrum Techniques and Applications.

Implementation of a Flexible LDPC Decoder

Guido Masera, Fabrizio Vacca, Federico Quaglio, 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

ASIP design for partially structured LDPC codes

Guido Masera, Libero Dinoi, Fabrizio Vacca, 2006 .

Interconnection framework for high-throughput, flexible LDPC decoders

Guido Masera, Alberto Tarable, Fabrizio Vacca, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Testing logic cores using a BIST P1500 compliant approach: a case of study

Paolo Bernardi, Guido Masera, Matteo Sonza Reorda, 2005, Design, Automation and Test in Europe.

A Flexible NTT-Based Multiplier for Post-Quantum Cryptography

G. Masera, P. Mazzetti, Maurizio Martina, 2023, IEEE Access.

Efficient Hardware Implementation of the LEDAcrypt Decoder

Guido Masera, Marco Baldi, Franco Chiaraluce, 2021, IEEE Access.

Chapter 13 – Hardware Design and Realization for Iteratively Decodable Codes

Guido Masera, Emmanuel Boutillon, E. Boutillon, 2014 .

NLCMAP: A Framework for the Efficient Mapping of Non-Linear Convolutional Neural Networks on FPGA Accelerators

M. R. Roch, S. Marsi, G. Masera, 2022, International Conference on Information Photonics.

HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures

C. Passerone, Nael Fasfous, W. Stechele, 2022, Electronics.

The ultimate limits of wireless networks

Yonina C. Eldar, Shlomo Shamai, Guido Masera, 2012 .

Reconfigurable coprocessor based JPEG 2000 implementation

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

Turbo NOC: A Framework for the Design of Network-on-Chip-Based Turbo Decoder Architectures

Guido Masera, Maurizio Martina, G. Masera, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks

Muhammad Abdullah Hanif, M. Shafique, G. Masera, 2019, 2020 International Joint Conference on Neural Networks (IJCNN).

High-Speed Logic Families Impact on Power Supply Noise Generation

Mariagrazia Graziano, Guido Masera, Maurizio Zamboni, 2001 .

Optimized VLSI Architecture of HEVC Fractional Pixel Interpolators with Approximate Computing

Guido Masera, Luca Valente, Maurizio Martina, 2020, Journal of Low Power Electronics and Applications.

State Metric Compression Techniques for Turbo Decoder Architectures

Guido Masera, Maurizio Martina, G. Masera, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

VLSI for Turbo Codes

Guido Masera, G. Masera, 2005 .

Turbo Decoder VLSI Architecture with Non-Recursive max* Operator for 3GPP LTE Standard

Guido Masera, Maurizio Martina, Ashfaq Ahmed, 2013 .

Architectural strategies for low-power VLSI turbo decoders

Gianluca Piccinini, Guido Masera, Maurizio Zamboni, 2002, IEEE Trans. Very Large Scale Integr. Syst..

VLSI architectures for turbo codes

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 1999, IEEE Trans. Very Large Scale Integr. Syst..

A 50 Mbit/s iterative turbo-decoder

Massimo Ruo Roch, Gianluca Piccinini, Guido Masera, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

Flexible blocks for high throughput serially concatenated convolutional codes

Guido Masera, Maurizio Martina, G. Masera, 2007, GLSVLSI '07.

Heterogeneous and opportunistic wireless networks

Yonina C. Eldar, Shlomo Shamai, Jordi Pérez-Romero, 2012 .