B. Parvais

发表

Comparative study of non-linearities in 28 nm node FDSOI and Bulk MOSFETs

V. Kilchytska, B. Kazemi Esfeh, C. Gimeno, 2017, 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

3D technologies for analog/RF applications

P. Wambacq, B. Parvais, A. Vandooren, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

The impact of sequential-3D integration on semiconductor scaling roadmap

B. Parvais, A. Vandooren, J. Ryckaert, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Semiconductor Technologies for next Generation Mobile Communications

P. Wambacq, B. Parvais, A. Vandooren, 2018, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A fully-integrated method for RTN parameter extraction

P. Wambacq, B. Parvais, G. Groeseneken, 2017, 2017 Symposium on VLSI Technology.

Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures

B. Parvais, B. Kaczer, D. Linten, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Advanced MOSFET variability and reliability characterization array

B. Parvais, G. Groeseneken, G. Gielen, 2015, 2015 IEEE International Integrated Reliability Workshop (IIRW).

Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications

B. Parvais, B. Kaczer, N. Collaert, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

A 40 nm LP CMOS PLL for high-speed mm-wave communication

P. Wambacq, B. Parvais, K. Scheir, 2010, 2010 Proceedings of ESSCIRC.

Defect-based compact modeling for RTN and BTI variability

B. Parvais, B. Kaczer, D. Verkest, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

P. Wambacq, B. Parvais, A. Mercha, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Key challenges and opportunities for 3D sequential integration

B. Parvais, A. Vandooren, J. Ryckaert, 2018, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Advanced Process Modules for (sub-) 45nm Analog/RF CMOS - Technology Description and Modeling Challenges

B. Parvais, A. Mercha, S. Decoutere, 2006, 2006 European Microwave Integrated Circuits Conference.

Perspectives of (sub-) 32nm CMOS for Analog/RF and mm-wave Applications

B. Parvais, G. Groeseneken, W. Sansen, 2008, 2008 European Microwave Integrated Circuit Conference.

A 10-Bit current-steering FinFET D/A converter

G. Knoblinger, F. Kuttner, D. Schmitt-Landsiedel, 2008, 2008 IEEE International SOI Conference.

Analysis of the FinFET parasitics for improved RF performances

B. Parvais, A. Mercha, S. Decoutere, 2007, 2007 IEEE International SOI Conference.

Suitability of FinFET technology for low-power mixed-signal applications

P. Wambacq, B. Parvais, R. Rooyackers, 2006, 2006 IEEE International Conference on IC Design and Technology.

Stochastic Matching Properties of FinFETs

B. Parvais, A. Mercha, S. Decoutere, 2006, IEEE Electron Device Letters.

A 6.6 mW inductorless static 2:1 frequency divider operating up to 60 GHz in 28 nm CMOS

P. Wambacq, B. Parvais, K. Vaesen, 2013, 2013 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS 2013).

60GHz transmitter front-end in 40nm LP-CMOS with improved back-off efficiency

P. Wambacq, B. Parvais, K. Vaesen, 2013, 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

B. Parvais, R. Rooyackers, A. Mercha, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells

B. Parvais, D. Verkest, Y. Sherazi, 2018, 2018 IEEE Symposium on VLSI Technology.

Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing

B. Parvais, S. Brebels, B. Govoreanu, 2021, 2021 Symposium on VLSI Circuits.

Highly scalable bulk FinFET Devices with Multi-VT options by conductive metal gate stack tuning for the 10-nm node and beyond

B. Parvais, A. Brand, N. Horiguchi, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET

B. Parvais, A. Mercha, S. Decoutere, 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

Perspective of RF design in future planar and FinFET CMOS

P. Wambacq, B. Parvais, A. Mercha, 2008, 2008 IEEE Radio Frequency Integrated Circuits Symposium.

First demonstration of III-V HBTs on 300 mm Si substrates using nano-ridge engineering

M. Ingels, B. Parvais, L. Witters, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Si/SiGe superlattice I/O finFETs in a vertically-stacked Gate-All-Around horizontal Nanowire Technology

B. Parvais, E. Simoen, G. Hellings, 2018, 2018 IEEE Symposium on VLSI Technology.

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

B. Parvais, B. Kaczer, E. Simoen, 2016, 2016 IEEE Symposium on VLSI Technology.

RMG nMOS 1st process enabling 10x lower gate resistivity in N7 bulk FinFETs

B. Parvais, S. Van Elshocht, A. Brand, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

Characterization, modeling, and optimization of FinFET MOS varactors

B. Parvais, A. Mercha, S. Decoutere, 2007, 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

CMOS-compatible GaN-based devices on 200mm-Si for RF applications: Integration and Performance

B. Parvais, E. Simoen, N. Waldron, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

MoM simulation of signal-to-noise patterns in infinite and finite receiving antenna arrays

B. Parvais, X. Dardenne, C. Craeye, 2004, IEEE Transactions on Antennas and Propagation.

A 52–66GHz subharmonically injection-locked quadrature oscillator with 10GHz locking range in 40nm LP CMOS

P. Wambacq, B. Parvais, K. Vaesen, 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

Small- and large-signal RF characterization of fully-depleted accumulation-mode varactors for low-voltage LC-VCO SOI design

B. Parvais, D. Flandre, D. Schreurs, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

B. Parvais, S. Biesemans, T. Schram, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Deep Submicron CMOS for Millimeter Wave Power Applications

B. Parvais, H. Zirath, S. Decoutere, 2008, IEEE Microwave and Wireless Components Letters.

A four-path 60GHz phased-array receiver with injection-locked LO, hybrid beamforming and analog baseband section in 90nm CMOS

P. Wambacq, B. Parvais, V. Szortyka, 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

B. Parvais, A. Vandooren, G. Hellings, 2018, 2018 IEEE Symposium on VLSI Technology.

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

B. Parvais, A. Vandooren, J. Ryckaert, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Determination and Validation of New Nonlinear FinFET Model Based on Lookup Tables

A. Caddemi, B. Parvais, A. Mercha, 2007, IEEE Microwave and Wireless Components Letters.

Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements

B. Kazemi Esfeh, B. Parvais, N. Planes, 2017, 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).