M. Haond

发表

Comparative study of non-linearities in 28 nm node FDSOI and Bulk MOSFETs

V. Kilchytska, B. Kazemi Esfeh, C. Gimeno, 2017, 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Issues for logic CMOS integration in systems on a chip (SoC)

M. Haond, 2000 .

20 nm FDSOI process and design platforms for high performance/ low power systems on chip

M. Haond, 2012, 2012 IEEE International SOI Conference (SOI).

28nm FDSOI technology platform for high-speed low-voltage digital applications

O. Rozeau, D. Noblet, M. Rafik, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Junction engineering for FDSOI technology speed/power enhancement

N. Planes, M. Haond, C. Fenouillet-Beranger, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Optimised Drain/Source Engineering for 0.35 μm NMOS Transistors

M. Haond, J.-L Ogier, 1993, ESSDERC '93: 23rd European solid State Device Research Conference.

Integration of Innovative Process Modules in a Full 0.35 μm CMOS Process and Circuit Demonstration

M. Haond, M. Lerme, 1994, ESSDERC '94: 24th European Solid State Device Research Conference.

Gate stack solutions in gate-first FDSOI technology to meet high performance, low leakage, VT centering and reliability criteria

X. Garros, J. Mazurier, M. Rafik, 2016, 2016 IEEE Symposium on VLSI Technology.

Ultra low capacitance measurements in multilevel metallisation CMOS by using a built-in electron-meter

M. Haond, J. Cluzel, F. Paillardet, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Analysis of width edge effects in advanced isolation schemes for deep submicron CMOS technologies

M. Haond, P. Sallagoity, M. Ada-Hanifi, 1996 .

Intrinsic gate capacitances of SOI MOSFETs: measurement, modelling, floating substrate effects

M. Haond, D. Flandre, P.G.A. Jespers, 1990, ESSDERC '90: 20th European Solid State Device Research Conference.

Selective CVD TiSi2 for Sub-0.5 μm N+/P+ CMOS Devices

M. Haond, J. L. Regolini, 1993, ESSDERC '93: 23rd European solid State Device Research Conference.

UTBB/FDSOI: Reasons for a success

M. Haond, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Analysis of S/D Engineering through Short Channel Effect and Hot Carrier Injection behavior in a 0.35μm CMOS Technology

M. Haond, N. Revil, E. Vandenbossche, 1996, ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference.

28 nm FD SOI Technology Platform RF FoM

V. Kilchytska, N. Planes, M. Haond, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment

J. Lacord, M. Haond, M. Casse, 2015, 2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

A novel dual isolation scheme for stress and back-bias maximum efficiency in FDSOI Technology

M. Vinet, F. Andrieu, M. Haond, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

14nm FDSOI technology for high speed and energy efficient applications

J. Mazurier, O. Faynot, A. Pofelski, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET

F. Andrieu, M. Haond, D. Dutartre, 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

The ADEQUAT project for development and transfer of 0.25 μm logic complementary metal–oxide–semiconductor modules

H. Ryssel, M. Haond, L. Van den hove, 1994 .

The ADEQUAT project for development and transfer of 0.25 μm logic CMOS modules

M. Haond, M. Rudan, R. De Keersmaecker, 1993, ESSDERC '93: 23rd European solid State Device Research Conference.

Comparative study of parasitic elements on RF FoM in 28 nm FD SOI and bulk technologies

V. Kilchytska, N. Planes, M. Haond, 2015, 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Fully depleted SOI: Achievements and future developments

M. Haond, 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

Measurement of intrinsic gate capacitances of SOI MOSFET's

M. Haond, D. Flandre, P.G.A. Jespers, 1990, IEEE Electron Device Letters.

Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications

V. Kilchytska, N. Planes, M. Haond, 2014, 2014 15th International Conference on Ultimate Integration on Silicon (ULIS).

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels

M. Haond, T. Skotnicki, S. Monfray, 2002, Digest. International Electron Devices Meeting,.

28 FDSOI analog and RF Figures of Merit at cryogenic temperatures

N. Planes, M. Haond, D. Flandre, 2018, 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Microanalysis of single‐crystal Si recrystallized using halogen lamps

M. Haond, D. Bensahel, M. Dupuy, 1983 .

Gate Oxide Breakdown in a SOI CMOS Process Usilng MESA Isolatioon

M. Haond, J. P. Gonchond, G. Mascarin, 1989, ESSDERC '89: 19th European Solid State Device Research Conference.

0.25 um NMOS transistor with nitride spacer: reduction of the short channel effect by optimisation of the gate reoxidation process and reliablity

M. Haond, N. Revil, M. Bonis, 1997, 27th European Solid-State Device Research Conference.

Insights in accesses optimization for nFET low temperature Fully Depleted Silicon On Insulator devices

G. Ghibaudo, P. Batude, M. Vinet, 2014, 2014 International Workshop on Junction Technology (IWJT).

Electrical transient study of negative resistance in SOI MOS transistors

M. Haond, O. Le Neel, 1990 .

28nm node bulk vs FDSOI reliability comparison

M. Rafik, N. Planes, M. Haond, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

Low frequency noise variability in high-k/metal gate stack 28nm bulk and FD-SOI CMOS transistors

G. Ghibaudo, N. Planes, M. Haond, 2011, 2011 International Electron Devices Meeting.

28-nm FDSOI nMOSFET RF Figures of Merits and Parasitic Elements Extraction at Cryogenic Temperature Down to 77 K

Denis Flandre, N. Planes, M. Haond, 2019, IEEE Journal of the Electron Devices Society.

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

Topographical dependence of charging and new phenomenon during inductively coupled plasma (ICP) CVD process

M. Haond, J. Carrere, J.-C. Oberlin, 2000, 2000 5th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.00TH8479).

A Cost-Effective Low Power Platform for the 45-nm Technology Node

R. Ranica, O. Callen, M. Haond, 2006, 2006 International Electron Devices Meeting.

Low frequency noise characterization of 0.25 μm Si CMOS transistors

M. Haond, Gerard Ghibaudo, G. Guégan, 1997 .

First integration of Ni0.9Co0.1 on pMOS transistors

P. Batude, M. Vinet, M. Haond, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

Lateral isolation in SOI CMOS technology

M. Haond, 1990, 1990 IEEE SOS/SOI Technology Conference. Proceedings.

28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures

B. Kazemi Esfeh, N. Planes, M. Haond, 2019, Solid-State Electronics.

High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator

O. Rozeau, G. Ghibaudo, P. Batude, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Electron-shading characterization in a HDP contact etching process using a patterned CHARM wafer

G. Reimbold, M. Haond, W. Lukaszek, 2000, 2000 5th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.00TH8479).

Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates

O. Faynot, F. Andrieu, N. Planes, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications

Denis Flandre, M. Haond, Jean-Pierre Raskin, 2014 .

High performance CMOS FDSOI devices activated at low temperature

J. Mazurier, G. Ghibaudo, P. Batude, 2016, 2016 IEEE Symposium on VLSI Technology.

nFET FDSOI activated by low temperature solid phase epitaxial regrowth: Optimization guidelines

G. Ghibaudo, P. Batude, M. Vinet, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

A Low Cost Drive Current Enhancement Technique Using Shallow Trench Isolation Induced Stress for 45-nm Node

M. Haond, G. Ribes, S. Vanbergue, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Improved Reliability With a New Plasma Nh3 Process for 0.35μιη P+ Poly-Gate Nitrided Oxide P-Mosfet's

M. Haond, Didier Goguenheim, Dominique Vuillaume, 1996 .

Highly-performant 38 nm SON (silicon-on-nothing) P-MOSFETs with 9 nm-thick channels

M. Haond, T. Skotnicki, S. Monfray, 2002, 2002 IEEE International SOI Conference.

Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs

A. Pofelski, M. Vinet, F. Andrieu, 2016, 2016 IEEE Symposium on VLSI Technology.

Impact of LDD structures on the operation of silicon MOSFETs at low temperature

M. Haond, Gerard Ghibaudo, I. M. Hafez, 1995 .

Manufacturability and Speed Performance Demonstration of Porous ULK (k=2.5) for a 45nm CMOS Platform

M. Haond, P. Ferreira, C. Cregut, 2007, 2007 IEEE Symposium on VLSI Technology.

First 80 nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance

M. Haond, T. Skotnicki, S. Monfray, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Effective defect entrainment in lamp zone melting of Si films on insulator

M. Haond, D. Dutartre, D. Bensahel, 1986 .

Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements

B. Kazemi Esfeh, B. Parvais, N. Planes, 2017, 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Rounded edge mesa for submicron SOI CMOS process

M. Haond, J. Galvier, O. Le Neel, 1990, ESSDERC '90: 20th European Solid State Device Research Conference.