M. Yanagisawa

发表

Logistic regression analysis of multiple interosseous hand-muscle activities using surface electromyography during finger-oriented tasks.

Masayuki Yokoyama, M. Yanagisawa, 2019, Journal of electromyography and kinesiology : official journal of the International Society of Electrophysiological Kinesiology.

Logistic Regression Analysis of Multiple Interosseous Hand-Muscle Activities using Surface Electromyography during Finger-Oriented Tasks

Masayuki Yokoyama, M. Yanagisawa, 2018, bioRxiv.

Regular Paper Scan Vulnerability in Elliptic Curve

T. Ohtsuki, M. Yanagisawa, Ryuta Nara, 2011 .

Implementation of Motion Estimation IP Core for MPEG Encoder

T. Ohtsuki, M. Yanagisawa, N. Togawa, 2001 .

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Nozomu Togawa, Masao Yanagisawa, Yuichiro Miyaoka, 2001 .

A hardware/software partitioning algorithm for SIMD processor cores

T. Ohtsuki, M. Yanagisawa, N. Togawa, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

A Hardware / Software Cosynthesis System for CAM Processors

T. Ohtsuki, M. Yanagisawa, N. Togawa, 2001 .

Indoor Navigation Based on Pedestrians ’ Viewpoints

M. Yanagisawa, N. Togawa, Ryota Iwanaji, 2016 .

Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching

Nozomu Togawa, Masao Yanagisawa, Yukiyasu Tsunoo, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks

Youhua Shi, Masao Yanagisawa, Lin Ye, 2019, 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow

Youhua Shi, Masao Yanagisawa, Jinghao Ye, 2021, IEEE Access.

Gesture recognition of air-tapping and its application to character input in VR space

Masao Yanagisawa, Masayuki Yokoyama, Mamoru Hirota, 2018, SIGGRAPH ASIA Posters.

Weighted adders with selector logics for super-resolution and its FPGA-based evaluation

Nozomu Togawa, Masao Yanagisawa, Hiromine Yoshihara, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution

Nozomu Togawa, Masao Yanagisawa, Hiromine Yoshihara, 2012, IPSJ Trans. Syst. LSI Des. Methodol..

Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Soft error tolerant latch designs with low power consumption (invited paper)

Saki Tajima, Youhua Shi, Nozomu Togawa, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A score-based classification method for identifying Hardware-Trojans at gate-level netlists

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Effective write-reduction method for MLC non-volatile memory

Nozomu Togawa, Masao Yanagisawa, Shinji Kimura, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

Nozomu Togawa, Masao Yanagisawa, Shinji Kimura, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A write-reducing and error-correcting code generation method for non-volatile memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A proposal for wearable controller device and finger gesture recognition using surface electromyography

Masao Yanagisawa, Masayuki Yokoyama, Mamoru Hirota, 2017, SIGGRAPH ASIA.

A high-level synthesis system for digital signal processing based on enumerating data-flow graphs

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

An Evaluation of Hand-Force Prediction Using Artificial Neural-Network Regression Models of Surface EMG Signals for Handwear Devices

Masao Yanagisawa, Masayuki Yokoyama, Ryohei Koyama, 2017, J. Sensors.

Hardware Trojans classification for gate-level netlists using multi-layer neural networks

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

A hardware-Trojan classification method utilizing boundary net structures

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2018, 2018 IEEE International Conference on Consumer Electronics (ICCE).

Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Linear and bi-linear interpolation circuits using selector logics and their evaluations

Nozomu Togawa, Masao Yanagisawa, Masashi Shio, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Hardware Trojans classification for gate-level netlists based on machine learning

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Small-sized and noise-reducing power analyzer design for low-power IoT devices

Nozomu Togawa, Masao Yanagisawa, Takashi Takenaka, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments

Masao Yanagisawa, Nozomu Togawa, Siya Bao, 2019, ICIS.

Dataflow Optimization through Exploring Single-Layer and Inter-Layer Data Reuse in Memory-Constrained Accelerators

M. Yanagisawa, Jinghao Ye, Youhua Shi, 2022, Electronics.

Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach

Nozomu Togawa, Masao Yanagisawa, Yuki Kobayashi, 2018, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

Instruction set and functional unit synthesis for SIMD processor cores

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Area/delay estimation for digital signal processor cores

M. Yanagisawa, T. Ohtsuki, Y. Miyaoka, 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

A hardware/software partitioning algorithm for processor cores of digital signal processing

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Scan-based attack against elliptic curve cryptosystems

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures

Masao Yanagisawa, Nozomu Togawa, Kento Hasegawa, 2020, IEICE Trans. Inf. Syst..

Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations

Nozomu Togawa, Masao Yanagisawa, Kazushi Kawamura, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2018, IPSJ Trans. Syst. LSI Des. Methodol..

A hardware/software cosynthesis system for digital signal processor cores with two types of register files

T. Ohtsuki, M. Yanagisawa, N. Togawa, 2000 .

Efficient Ising Model Mapping to Solving Slot Placement Problem

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2019, 2019 IEEE International Conference on Consumer Electronics (ICCE).

An Ising model mapping to solve rectangle packing problem

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

New correction algorithms for multiple comparisons in case-control multilocus association studies based on haplotypes and diplotype configurations

Masao Yanagisawa, Yusuke Nakamura, Naoyuki Kamatani, 2008, Journal of Human Genetics.