Fu-Yi Tsai

Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

Ming-Dou Ker, Chia-Tsen Dai, Po-Yen Chiu, 2012, 2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

Ming-Dou Ker, Yeong-Jar Chang, Po-Yen Chiu, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Ming-Dou Ker, Yeong-Jar Chang, Po-Yen Chiu, 2009, 2009 IEEE International Reliability Physics Symposium.