Woo-Seop Kim

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems

J. Kennedy, R. Mooney, R. Ellis, 2005, IEEE Journal of Solid-State Circuits.

A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

Woo-Seop Kim, Kyu-hyoun Kim, Young-Soo Sohn, 2006 .

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

Jung-Hwan Choi, Woo-Seop Kim, Changhyun Kim, 2005, IEEE Journal of Solid-State Circuits.