Chih-Ping Chen

Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device

Bing-Yue Tsui, Yi-Hsuan Hsiao, Hang-Ting Lue, 2012, 2012 International Electron Devices Meeting.

Study of fast initial charge loss and it's impact on the programmed states Vt distribution of charge-trapping NAND Flash

Kuo-Pin Chang, Hang-Ting Lue, Chih-Chang Hsieh, 2010, 2010 International Electron Devices Meeting.

Radically extending the cycling endurance of Flash memory (to > 100M Cycles) by using built-in thermal annealing to self-heal the stress-induced damage

Yi-Hsuan Hsiao, Hang-Ting Lue, Chih-Chang Hsieh, 2012, 2012 International Electron Devices Meeting.

A Survey of 3 D Nand Flash Memory

Y. Shih, K. Hsieh, Y. Hsiao, 2013 .

A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability

K. Hsieh, Chih-Yuan Lu, H. Lue, 2010, 2010 International Electron Devices Meeting.

A 128Gb (MLC)/192Gb (TLC) single-gate vertical channel (SGVC) architecture 3D NAND using only 16 layers with robust read disturb, long-retention and excellent scaling capability

Kuo-Pin Chang, Tahone Yang, Y. J. Chen, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).