G. Cho

TCAD Simulation of Data Retention Characteristics of Charge Trap Device for 3-D NAND Flash Memory

Sungjoo Hong, Sungkye Park, Gyuseog Cho, 2015, 2015 IEEE International Memory Workshop (IMW).

Characterization of Polymetal Gate Transistors With Low-Temperature Atomic-Layer-Deposition-Grown Oxide Spacer

Ga-Won Lee, Sung-Joo Hong, K. Lim, 2009 .

Novel Program Method of String Select Transistors for Layer Selection in Channel-Stacked NAND Flash Memory

J. Y. Seo, D. Kwon, Byung-Gook Park, 2016, IEEE Transactions on Electron Devices.

Effects of abnormal cell-to-cell interference on p-type floating gate and control gate NAND flash memory

Woo Young Choi, Sung-Kye Park, Byungin Lee, 2014 .

Investigation of Vertical Channel Architecture for Bulk Erase Operation in Three-Dimensional NAND Flash Memory

Eun-seok Choi, Sung-Kye Park, Gae-hun Lee, 2012 .

A Novel 3D Cell Array Architecture for Terra-Bit NAND Flash Memory

Eun-Seok Choi, Sung-Kye Park, Gyu-Seog Cho, 2011, 2011 3rd IEEE International Memory Workshop (IMW).