L. Risch

发表

20 nm tri-gate SONOS memory cells with multi-level operation

H. Reisinger, L. Dreeskornfeld, J. Hartwich, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Nanoscale FinFETs for low power applications

R. J. Luyken, F. Hofmann, W. Pamler, 2003, International Semiconductor Device Research Symposium, 2003.

Characterization of SiGe quantum-well p-channel MOSFETs

F. Hofmann, K. Hofmann, L. Risch, 1995 .

Drain leakage mechanisms in fully depleted SOI devices with undoped channel [MOSFETs]

L. Dreeskornfeld, J. Hartwich, L. Risch, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Channel Engineering using RP-CVD Epitaxy for High Performance CMOS Transistors

F. Hofmann, H. Schafer, M. Franosch, 1996, ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference.

Use of LPCVD TEOS as a direct bonding material for layer transfer: densified vs. undensified

F. Hofmann, W. Weber, W. Hansch, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Retention time of novel charge trapping memories using Al/sub 2/O/sub 3/ dielectrics

R. J. Luyken, F. Hofmann, H. Reisinger, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Modelling and Fabrication of a P-Channel SiGe-MOSFET with Very High Mobility and Transconductance

F. Hofmann, H. Schafer, K. Hofmann, 1994 .

Characterization of ultra-thin SOI transistors down to the 20 nm gate length regime with scanning spreading resistance microscopy (SSRM)

W. Vandervorst, M. Specht, L. Dreeskornfeld, 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..

Short-channel vertical sidewall MOSFETs

U. Langmann, A. Korbel, Lothar Risch, 2001 .

Vertical Si-Metal-Oxide-Semiconductor Field Effect Transistors with Channel Lengths of 50 nm by Molecular Beam Epitaxy.

H. Gossner, I. Eisele, L. Risch, 1994 .

Charge trapping memory structures with Al2O3 trapping dielectric for high-temperature applications

Michael Specht, Franz Hofmann, Wolfgang Rösner, 2005 .

Fabrication of a nano-scale NAND memory array based on a SONOS Fin-FET cell using e-beam lithography and hydrogen-silsesquioxane resist

J. Kretz, W. Weber, M. Specht, 2007 .

Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications

H. Reisinger, L. Dreeskornfeld, W. Weber, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Vertical MOS Transistors with 70nm Channel Length

L. Risch, H. Schafer, F. Hofmann, 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

Influence of crystal orientation and body doping on trigate transistor performance

Michael Specht, Erhard Landgraf, Wolfgang Rösner, 2006 .

Circuit arrangement having single-electron components, process for their operation and use of the method for addition of binary numbers

L. Risch, W. Roesner, Ties Ramcke, 1997 .

Electron mobility in short-channel MOSFET's with series resistances

L. Risch, L. Risch, 1983, IEEE Transactions on Electron Devices.

Short-channel MOS transistors in the avalanche-multiplication regime

L. Risch, A. Schutz, L. Risch, 1982, IEEE Transactions on Electron Devices.

Pushing CMOS beyond the roadmap

L. Risch, L. Risch, 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

Fabrication of ultra-thin-film SOI transistors using the recessed channel concept

R. J. Luyken, F. Hofmann, T. Schulz, 2005 .

Electron beam lithography for nanometer-scale planar double-gate transistors

W. Hansch, J. Kretz, W. Weber, 2005 .

Ultrasmall Pt clusters for single electron tunneling studies

F. Hofmann, H. Hoffmann, F. Kreupl, 1996 .

Novel dual bit tri-gate charge trapping memory devices

H. Reisinger, L. Dreeskornfeld, J. Hartwich, 2004, IEEE Electron Device Letters.