Jonathan Chang

发表

Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions

Vivek De, David Stoppa, Jonathan Chang, 2015, IEEE J. Solid State Circuits.

A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications

Min Cao, Sreedhar Natarajan, Hank Cheng, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Embedded Micro-detectors for EUV Exposure Control in FinFET CMOS Technology

Y. Chih, Y. King, C. Lin, 2022, Nanoscale Research Letters.

Memory-Logic Hybrid Gate With 3-D Stackable Complementary Latches

Y. Chih, Y. King, Jonathan Chang, 2020, IEEE Transactions on Electron Devices.

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination

David Blaauw, Dennis Sylvester, Yu-Der Chih, 2019, IEEE Journal of Solid-State Circuits.

13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

Sreedhar Natarajan, Shien-Yang Wu, Hung-Jen Liao, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Reliability evaluation of an extreme TSV interposer and interconnects for the 20nm technology CoWoS IC package

Jonathan Chang, Laurene Yip, Suresh Ramalingam, 2015, 2015 IEEE 65th Electronic Components and Technology Conference (ECTC).

A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS

Mahmut E. Sinangil, Rawan Naous, Yih Wang, 2021, IEEE Journal of Solid-State Circuits.

A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell

Mahmut E. Sinangil, Hung-Jen Liao, Yen-Ting Lin, 2019, IEEE Journal of Solid-State Circuits.

A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process

Y. Chih, Chieh-Pu Lo, H. Chuang, 2020, 2020 IEEE International Electron Devices Meeting (IEDM).

Detectors Array for In Situ Electron Beam Imaging by 16-nm FinFET CMOS Technology

Y. Chih, Y. King, C. Lin, 2021, Nanoscale Research Letters.

Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology

Chien-Ping Wang, Ying-Chun Shen, Peng-Chun Liou, 2019, Sensors.

High Resolution Ion Detector (HRID) by 16nm FinFET CMOS Technology

Peng-Chun Liou, Yu-Lun Chueh, Jonathan Chang, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

Hidehiro Fujiwara, Po-Yi Huang, Jonathan Chang, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 16 nm 128 Mb SRAM in High- $\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications

Jonathan Chang, Shien-Yang Wu, Hung-Jen Liao, 2014, IEEE Journal of Solid-State Circuits.

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

Hidehiro Fujiwara, Jonathan Chang, Shien-Yang Wu, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

Jonathan Chang, Qing Dong, Hung-Jen Liao, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

Hidehiro Fujiwara, Hung-Jen Liao, Yen-Huei Chen, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications

Jonathan Chang, Michael Clinton, Hank Cheng, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications

Jonathan Chang, Hung-Jen Liao, Ching-Wei Wu, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies

Hidehiro Fujiwara, Jonathan Chang, Shien-Yang Wu, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS

Jonathan Chang, Ming-Hung Chang, Hung-Jen Liao, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications

Hidehiro Fujiwara, Jonathan Chang, Hung-Jen Liao, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Test structures for debugging variation of critical devices caused by layout-dependent effects in FinFETs

Jonathan Chang, Qi Lin, Hans Pan, 2018, 2018 IEEE International Conference on Microelectronic Test Structures (ICMTS).

Product Lifetime Estimation in 7nm with Large data of Failure Rate and Si-Based Thermal Coupling Model

Jonathan Chang, Rhesa Nathanael, Jae-Gyung Ahn, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

Enabling a Manufacturable 3D Technologies and Ecosystem using 28nm FPGA with Stack Silicon Interconnect Technology

Suresh Ramalingam, Steve Chiu, Liam Madden, 2013 .

3DIC developments for high yield and reliability manufacturing

Jonathan Chang, Suresh Ramalingam, Xin Wu, 2017, 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).