K. Kishine

A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

Keiji Kishine, Haruhiko Ichino, H. Ichino, 2002 .

10.3 Gbit/s burst-mode PIN-TIA module with high sensitivity, wide dynamic range and quick response

Keiji Kishine, Kazuyoshi Nishimura, Shunji Kimura, 2008 .

A 10G Burst-Mode PIN-TIA Module with 10-nsec Response for PON Systems

N. Yoshimoto, S. Kimura, S. Nishihara, 2007, LEOS 2007 - IEEE Lasers and Electro-Optics Society Annual Meeting Conference Proceedings.

Capacitive Sensor for Contact Angle Estimation of Droplet on Microfluidic Chip

A. Tsuchiya, K. Kishine, Toshiyuki Inoue, 2019, 2019 IEEE Asia-Pacific Microwave Conference (APMC).

Throughput Estimation Method in Burst ACK Scheme for Optimizing Frame Size and Burst Frame Number Appropriate to SNR-Related Error Rate

Keiji Kishine, Shoko Ohteru, K. Kishine, 2010, IEICE Trans. Commun..

MAC protocol based on cross-layer design methodology for fast link in wireless communication systems

Keiji Kishine, Haruhiko Ichino, Shoko Ohteru, 2007, IEICE Electron. Express.

Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA

Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, 2021, 2021 International Conference on Electronics, Information, and Communication (ICEIC).

A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit

Keiji Kishine, Haruhiko Ichino, Kiyoshi Ishii, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS

Hidetoshi Onodera, Hiroshi Inoue, Akira Tsuchiya, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.