Y. Ochiai

45-nm gate length CMOS technology and beyond using steep halo

T. Fukai, H. Wakabayashi, T. Matsuda, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Nano-net fabrication on the glass capillary by focused-ion-beam chemical-vapor-deposition

T. Hoshino, T. Kaito, Jun-ichi Fujita, 2005, The 13th International Conference on Solid-State Sensors, Actuators and Microsystems, 2005. Digest of Technical Papers. TRANSDUCERS '05..

High performance carbon-nanotube field-effect transistors

H. Hongo, M. Yudasaka, S. Iijima, 2003, Digest of Papers Microprocesses and Nanotechnology 2003. 2003 International Microprocesses and Nanotechnology Conference.

A 0.10-/spl mu/m CMOS device with a 40-nm gate sidewall and multilevel interconnects for system LSI

T. Fukai, H. Wakabayashi, Y. Nakahara, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Bilayer Resist Method for Room-Temperature Nanoimprint Lithography

M. Sasago, K. Watanabe, H. Namatsu, 2003, Digest of Papers Microprocesses and Nanotechnology 2003. 2003 International Microprocesses and Nanotechnology Conference.

Transistor operation of 30-nm gate-length EJ-MOSFETs

T. Sakamoto, J. Sone, T. Baba, 1998, IEEE Electron Device Letters.

Sub-10-nm planar-bulk-CMOS devices using lateral junction control

A. Ogura, H. Wakabayashi, T. Mogami, 2003, IEEE International Electron Devices Meeting 2003.

Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

H. Kawaura, H. Wakabayashi, M. Hane, 2006, IEEE Transactions on Electron Devices.