C. Bowen

Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process

G.A. Brown, A. Chatterjee, M. Rodder, 1997, International Electron Devices Meeting. IEDM Technical Digest.

The Current Understanding of the Trap Generation Mechanisms that Lead to the Power Law Model for Gate Dielectric Breakdown

A.T. Krishnan, P. Nicollian, R. Khamankar, 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

Exploring Transistor Width Effect on Stress-induced Performance Improvement in PMOSFET with SiGe Source/Drain

Xin Wang, C. Bowen, M. Huang, 2005, 2005 International Conference On Simulation of Semiconductor Processes and Devices.

Physical oxide thickness extraction and verification using quantum mechanical simulation

G. Klimeck, A. Chatterjee, Gerhard Klimeck, 1997, International Electron Devices Meeting. IEDM Technical Digest.

45-nm node NiSi FUSI on nitrided oxide bulk CMOS fabricated by a novel integration process

F. Mehrad, H. Bu, L. Colombo, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

B. Hornung, C. Machala, A. Krishnan, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..