I.-C. Chen

发表

Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process

G.A. Brown, A. Chatterjee, M. Rodder, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Interface trap-enhanced gate-induced leakage current in MOSFET

C.W. Teng, D.J. Coleman, I. Chen, 1989, IEEE Electron Device Letters.

A shallow trench isolation using LOCOS edge for preventing corner effects for 0.25/0.18 /spl mu/m CMOS technologies and beyond

A. Chatterjee, D. Rogers, I. Ali, 1996, International Electron Devices Meeting. Technical Digest.

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator

G.A. Brown, A. Chatterjee, M. Rodder, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Feasibility of using W/TiN as metal gate for conventional 0.13 /spl mu/m CMOS technology and beyond

A. Chatterjee, M. Rodder, R. Chapman, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Physical oxide thickness extraction and verification using quantum mechanical simulation

G. Klimeck, A. Chatterjee, Gerhard Klimeck, 1997, International Electron Devices Meeting. IEDM Technical Digest.

A shallow trench isolation for sub-0.13 /spl mu/m CMOS technologies

A. Amerasekera, M. Nandakumar, P. Mei, 1997, International Electron Devices Meeting. IEDM Technical Digest.

A 0.25 /spl mu/m gate length CMOS technology for 1V low power applications-device design and power/performance considerations

M. Nandakumar, A. Chatterjee, I.-C. Chen, 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.

Performance and reliability enhancement for CVD tungsten polycided CMOS transistors due to fluorine incorporation in the gate oxide

M. Rodder, I.-C. Chen, H.-J. Wann, 1994, IEEE Electron Device Letters.

Gate current injection initiated by electron band-to-band tunneling in MOS devices

C.W. Teng, D.J. Coleman, I.-C. Chen, 1989, IEEE Electron Device Letters.

Comparison between CVD and thermal oxide dielectric integrity

C. Hu, I. Chen, J. Lee, 1986, IEEE Electron Device Letters.

Low resistance Ti or Co salicided raised source/drain transistors for sub-0.13 /spl mu/m CMOS technologies

M. Nandakumar, J. Kittl, K. Violette, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Effects of poly depletion on the estimate of thin dielectric lifetime

S.J. Wang, I. Chen, H. Tigelaar, 1991, IEEE Electron Device Letters.

A pocket implant model for sub-0.18 micron CMOS process flows

M. Nandakumar, K. Vasanth, M. Rodder, 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.

A comparison of TiN processes for CVD W/TiN gate electrode on 3 nm gate oxide

G.A. Brown, J. D. Luttmer, R. Chapman, 1997, International Electron Devices Meeting. IEDM Technical Digest.