N. Singh

发表

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

S.C. Rustagi, R. Kumar, N. Balasubramanian, 2006, IEEE Electron Device Letters.

Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors

S.C. Rustagi, N. Balasubramanian, N. Singh, 2007, IEEE Electron Device Letters.

Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

S.C. Rustagi, N. Balasubramanian, N. Singh, 2006, 2006 International Electron Devices Meeting.

Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell

S.H.G. Teo, N. Balasubramanian, E. Gnani, 2008, IEEE Electron Device Letters.

Gate-All-Around Junctionless Nanowire MOSFET With Improved Low-Frequency Noise Behavior

Jianmin Miao, Dim-Lee Kwong, Woo-Tae Park, 2011, IEEE Electron Device Letters.

Observation of Metal-Layer Stress on Si Nanowires in Gate-All-Around High- $\kappa$/Metal-Gate Device Structures

S.C. Rustagi, S.H.G. Teo, N. Balasubramanian, 2007, IEEE Electron Device Letters.

Nickel Salicided Source/Drain Extensions for Performance Improvement in Ultrascaled (Sub 10 nm) Si-Nanowire Transistors

N. Singh, D. Kwong, D. Chan, 2009, IEEE Electron Device Letters.

Grain-Orientation Induced Quantum Confinement Variation in FinFETs and Multi-Gate Ultra-Thin Body CMOS Devices and Implications for Digital Design

K. Endo, J. F. Chen, S. H. Rasouli, 2011, IEEE Transactions on Electron Devices.

Nanowire FETs for low power CMOS applications featuring novel gate-all-around single metal FUSI gates with dual Φm and VT tune-ability

N. Singh, G. Lo, D. Kwong, 2008, 2008 IEEE International Electron Devices Meeting.

CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach

S.C. Rustagi, S.H.G. Teo, N. Balasubramanian, 2007, IEEE Electron Device Letters.

Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory

S.H.G. Teo, N. Balasubramanian, M.B. Yu, 2007, 2007 IEEE International Electron Devices Meeting.

Vertical-Si-Nanowire SONOS Memory for Ultrahigh-Density Application

Guo-Qiang Lo, Dim-Lee Kwong, Hong Yu Yu, 2009, IEEE Electron Device Letters.

Numerical investigation on the junctionless nanowire FET

A. Gnudi, S. Reggiani, E. Gnani, 2011, Ulis 2011 Ultimate Integration on Silicon.

Vertically Stacked and Independently Controlled Twin-Gate MOSFETs on a Single Si Nanowire

Guo-Qiang Lo, Dim-Lee Kwong, Nansheng Shen, 2011, IEEE Electron Device Letters.

Omega-Gate p-MOSFET With Nanowirelike SiGe/Si Core/Shell Channel

D.S.H. Chan, D.-L. Kwong, N. Singh, 2009, IEEE Electron Device Letters.

A Bistable Silicon Nanofin: An Ideal Device for Nonvolatile Memory Applications

Chengkuo Lee, Bo Woon Soon, N. Singh, 2013, IEEE Nanotechnology Magazine.

Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs in the Subthreshold Region

Yong-Zhong Xiong, Xing Zhou, S.C. Rustagi, 2009, IEEE Electron Device Letters.

CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs

S.H.G. Teo, B. Yang, K. Buddharaju, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Impact of Gate Electrodes on $\hbox{1}/f$ Noise of Gate-All-Around Silicon Nanowire Transistors

Yong-Zhong Xiong, Xing Zhou, S.C. Rustagi, 2009, IEEE Electron Device Letters.

Random Telegraph Signal Noise in Gate-All-Around Si-FinFET With Ultranarrow Body

D.S.H. Chan, N. Balasubramanian, N. Singh, 2006, IEEE Electron Device Letters.

Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

S.C. Rustagi, S.H.G. Teo, N. Balasubramanian, 2007, ESSDERC 2007 - 37th European Solid State Device Research Conference.

Low-Temperature Transport Characteristics and Quantum-Confinement Effects in Gate-All-Around Si-Nanowire N-MOSFET

S.C. Rustagi, N. Balasubramanian, N. Singh, 2007, IEEE Electron Device Letters.

Si, SiGe Nanowire Devices by Top–Down Technology and Their Applications

S.C. Rustagi, N. Balasubramanian, K. Buddharaju, 2008, IEEE Transactions on Electron Devices.

Polycrystalline Si Nanowire SONOS Nonvolatile Memory Cell Fabricated on a Gate-All-Around (GAA) Channel Architecture

D.L. Kwong, N. Singh, G.Q. Lo, 2009, IEEE Electron Device Letters.

Improved Vertical Silicon Nanowire Based Thermoelectric Power Generator With Polyimide Filling

Yida Li, B. C. Tinh, K. Buddharaju, 2012, IEEE Electron Device Letters.

Highly compact 1T-1R architecture (4F2 footprint) involving fully CMOS compatible vertical GAA nano-pillar transistors and oxide-based RRAM cells exhibiting excellent NVM properties and ultra-low power operation

X. Li, B. Gao, A. Kamath, 2012, 2012 International Electron Devices Meeting.

Performance breakthrough in 8 nm gate length Gate-All-Around nanowire transistors using metallic nanowire contacts

D.S.H. Chan, D.L. Kwong, N. Singh, 2008, 2008 Symposium on VLSI Technology.

Improved carrier injection in gate-all-around Schottky barrier silicon nanowire field-effect transistors

Guo-Qiang Lo, Jianwei Peng, S. J. Lee, 2008 .

Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

N. Singh, G. Lo, D. Kwong, 2009, IEEE Electron Device Letters.