T. Kuwata

A 0.13 /spl mu/m CMOS technology integrating high-speed and low-power/high-density devices with two different well/channel structures

A. Ono, K. Imai, K. Noda, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Design and measurements of test element group wafer thinned to 10 /spl mu/m for 3D system in package

T. Kuwata, A. Ikeda, S. Kajiwara, 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).