Chau-Neng Wu

Area-efficient layout design for output transistors with consideration of ESD reliability

Chung-Yu Wu, Ming-Dou Ker, Hun-Hsien Chang, 1996, Proceedings 1996 IEEE Hong Kong Electron Devices Meeting.

THE MIXED-VOLTAGE PROCESS

Chau-Neng Wu, Michang Chang, 2003 .

Latch-up failure path between power pins in the mixed-voltage process

Chau-Neng Wu, H.-M. Chou, M. Chang, 2003, IEEE International Integrated Reliability Workshop Final Report, 2003.

ESD protection for slew-rate-controlled output buffer in a 0.5 μm CMOS SRAM technology

Ming-Dou Ker, Chau-Neng Wu, 1998 .

Efficient Output Esd Protection Of High-speed Sram Ic With Well-coupled Technique In Sub-pm Cmos Technology

Ming-Dou Ker, Chau-Neng Wu, Ta-Lee Yu, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

Efficient output ESD protection for 0.5-/spl mu/m high-speed CMOS SRAM IC with well-coupled technique

Ming-Dou Ker, Chau-Neng Wu, 1996 .

ESD protection for output pad with well-coupled field-oxide device in 0.5-/spl mu/m CMOS technology

Ming-Dou Ker, Chau-Neng Wu, 1997 .