Ta-Lee Yu

Area-efficient layout design for output transistors with consideration of ESD reliability

Chung-Yu Wu, Ming-Dou Ker, Hun-Hsien Chang, 1996, Proceedings 1996 IEEE Hong Kong Electron Devices Meeting.

Hot Carrier Reliability Considerations For High Performance Submicron Mosfet's

Ta-Lee Yu, Jiuun-Jer Yang, Honda Huang, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

A novel ESD protection circuit for ultra-deep-submicron low power mixed-signal IC designs

J. Ji, Ta-Lee Yu, Jing Liu, 2007, 2007 7th International Conference on ASIC.

Efficient Output Esd Protection Of High-speed Sram Ic With Well-coupled Technique In Sub-pm Cmos Technology

Ming-Dou Ker, Chau-Neng Wu, Ta-Lee Yu, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

Chung-Yu Wu, Ming-Dou Ker, Tao Cheng, 1994, Proceedings of 1994 IEEE International Integrated Reliability Workshop (IRWS).

ESD protection to overcome internal gate oxide damage on digital-analog interface of mixed-mode CMOS IC's

Ming-Dou Ker, Ta-Lee Yu, 1996 .

Efficient layout style of CMOS output buffer to improve driving capability of low-voltage submicron CMOS IC's

Ming-Dou Ker, Tao Cheng, Hun-Hsien Chang, 1995, Proceedings of 4th International Conference on Solid-State and IC Technology.

ESD protection to overcome internal gate oxide damage on digital-analog interface of mixed-mode CMOS IC's

Ming-Dou Ker, Ta-Lee Yu, 1996, Proceedings of the 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.