Kuang-Hsin Chen

Modeling isolation-induced mechanical stress effect on SOI MOS devices

Ke-Wei Su, Di-Hong Lee, Chien-Chao Huang, 2003, 2003 IEEE International Conference on SOI.

A 65nm node strained SOI technology with slim spacer

Chenming Hu, Tsai-Sheng Gau, Yee-Chia Yeo, 2003, IEEE International Electron Devices Meeting 2003.

45nm Node Planar-SO1 Technology with 0.296pm2 6T-SUM Cell

Chenming Hu, Mong-Song Liang, Di-Hong Lee, 2004 .

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

Chenming Hu, Tsai-Sheng Gau, Jaw-Jung Shin, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..