Tomonori Sekiguchi

发表

A 29-ns 64-Mb DRAM with hierarchical array architecture

Masayuki Nakamura, Takesada Akiba, Kazuhiko Kajigaya, 1995 .

A low-impedance open-bitline array for multigigabit DRAM

Kiyoo Itoh, Masayuki Nakamura, Kazuhiko Kajigaya, 2002 .

Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays

Kiyoo Itoh, Satoru Akiyama, Tomonori Sekiguchi, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays

Kiyoo Itoh, Tomonori Sekiguchi, Yoshimitsu Yanagawa, 2012, IEICE Trans. Electron..

A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing

Kiyoo Itoh, Satoru Akiyama, Tomonori Sekiguchi, 2012, IEICE Trans. Electron..

Calculation of the Potential Distribution around an Impurity-Atom-Wire-The Validity of the Thomas-Fermi Approximation

Tomonori Sekiguchi, Kazuhito Furuya, 1993 .

Low-noise, high-speed data transmission using a ringing-canceling output buffer

Masashi Horiguchi, Takeshi Sakata, M. Aoki, 1995 .

0.5-V Low-$V _{\rm T}$ CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays

Satoru Akiyama, Tomonori Sekiguchi, Yoshimitsu Yanagawa, 2010, IEEE Journal of Solid-State Circuits.

A High-Endurance Read/Write Scheme for Half-V~c~c Plate Nonvolatile DRAMs with Ferroelectric Capacitors

Takeshi Sakata, Kazuhiko Kajigaya, Katsutaka Kimura, 2001 .

An experimental 220 MHz 1 Gb DRAM

Masashi Horiguchi, Takeshi Sakata, Fumio Murai, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation

Kiyoo Itoh, Satoru Akiyama, Takayuki Kawahara, 2007, IEICE Trans. Electron..

10.2 A 22ng/√Hz 17mW MEMS Accelerometer with Digital Noise-Reduction Techniques

Akira Matsumoto, Atsushi Isobe, Takashi Oshima, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 22-ng/ $\surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction Techniques

Akira Matsumoto, Atsushi Isobe, Taizo Yamawaki, 2020, IEEE Journal of Solid-State Circuits.

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

Takeshi Sakata, Eiji Takeda, Mayu Aoki, 1995, IEEE J. Solid State Circuits.

Low-power chip interconnection by dynamic termination

Takayuki Kawahara, Katsutaka Kimura, Masashi Horiguchi, 1995 .

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup

Takeshi Sakata, Takayuki Kawahara, Kazuhiko Kajigaya, 2005, IEEE International Conference on Communications, 2005. ICC 2005. 2005.

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing

Tomonori Sekiguchi, Yoshimitsu Yanagawa, Kazuo Ono, 2011, IEEE Journal of Solid-State Circuits.

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory

Takeshi Sakata, Kazuhiko Kajigaya, Katsutaka Kimura, 1997 .

MEMS Gyroscope With Less Than 1-deg/h Bias Instability Variation in Temperature Range From −40 °C to 125 °C

Tomonori Sekiguchi, Masatoshi Kanamaru, Masahide Hayashi, 2018, IEEE Sensors Journal.

Capacitive MEMS Accelerometer With Perforated and Electrically Separated Mass Structure for Low Noise and Low Power

Atsushi Isobe, Takashi Oshima, Tomonori Sekiguchi, 2019, Journal of Microelectromechanical Systems.

MEMS Gyroscope With Concentrated Springs Suspensions Demonstrating Single Digit Frequency Split and Temperature Robustness

Andrei M. Shkel, Tomonori Sekiguchi, T. Sekiguchi, 2019, Journal of Microelectromechanical Systems.

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

T. Takahashi, T. Matano, S. Miyatake, 2002, VLSIC 2002.

A low-cost, 30 NG/VHZ noise floor MEMS accelerometers for large sensor network

Chisaki Takubo, Atsushi Isobe, Takashi Oshima, 2018, 2018 IEEE Micro Electro Mechanical Systems (MEMS).

Design of Perforated Membrane for Low-Noise Capacitive MEMS Accelerometers

Chisaki Takubo, Atsushi Isobe, Takashi Oshima, 2018, 2018 IEEE SENSORS.

Low-V_T CMOS Preamplifier for 0.5-V Gigabit-DRAM Arrays

Satoru Akiyama, Tomonori Sekiguchi, Yoshimitsu Yanagawa, 2010 .

A 0.5-V FD-SOI Twin-Cell DRAM with Offset-Free Dynamic-VT Sense Amplifiers

Kiyoo Itoh, Tomonori Sekiguchi, Riichiro Takemura, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Low Power Chip Interconnection by Dynamic Termination

Masashi Horiguchi, Takayuki Kawahara, Tomonori Sekiguchi, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

CMOS low-VT preamplifier for 0.5-V gigabit-DRAM arrays

Satoru Akiyama, Tomonori Sekiguchi, Yoshimitsu Yanagawa, 2009, 2009 IEEE Asian Solid-State Circuits Conference.