Toshikazu Tachibana

A 29-ns 64-Mb DRAM with hierarchical array architecture

Masayuki Nakamura, Takesada Akiba, Kazuhiko Kajigaya, 1995 .

256 Mb DRAM technologies for file applications

Masashi Horiguchi, Takashi Nishida, Norio Hasegawa, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 256-Mb Double-Data-Rate SDRAM with a 10-mW Analog DLL Circuit

Yasushi Kawase, Takesada Akiba, Yoshinobu Nakagome, 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

256-Mb DRAM circuit technologies for file applications

Masashi Horiguchi, Takashi Nishida, Norio Hasegawa, 1993 .