P. Morin

Low temperature process flow optimisation for 65nm CMOS mixed-signal applications

B. Tavel, M. Bidaud, M. Denais, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

A method to determine the Young's modulus of thin-film elements assisted by dark-field electron holography

Shay Reboh, Martin Hÿtch, A. Claverie, 2013 .

Modeling the dark current histogram induced by gold contamination in complementary-metal-oxide-semiconductor image sensors

D. Bauza, Florian Domengie, D. Bauza, 2015 .

Electrical characterization and mechanical modeling of process induced strain in 65 nm CMOS technology

S. Orain, C. Ortolland, P. Stolk, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

A functional 0.69 /spl mu/m/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform

J. Farkas, N. Planes, N. Revil, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Elastic properties of tensile nitrogen-plasma-treated multilayer silicon nitride films

F. Volpi, Muriel Braccini, Daniel Benoit, 2014 .

Design technology co-optimization of 3D-monolithic standard cells and SRAM exploiting dynamic back-bias for ultra-low-voltage operation

O. Rozeau, G. Cibrario, P. Batude, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Characterisation of silicon nitride thin films used as stressor liners on CMOS FETs

F. Volpi, M. Braccini, P. Morin, 2008, 2008 9th International Conference on Ultimate Integration of Silicon.

Gate stack optimization for 65 nm CMOS low power and high performance platform

R. Palla, B. Tavel, C. Ortolland, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..