Kaushik Roy

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An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective

Kaushik Roy, Jing Li, Patrick Ndai, 2009, ASP-DAC.

Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM

Chip-Hong Chang, Kaushik Roy, Le Zhang, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Photonic Spiking Neural Networks - From Devices to Systems pdf

Kaushik Roy, Indranil Chakraborty, Gobinda Saha, 2018, ArXiv.

Fast, low power evaluation of elementary functions using radial basis function networks

Kaushik Roy, Parami Wijesinghe, Chamika M. Liyanagedera, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic Computing

Kaushik Roy, Gopalakrishnan Srinivasan, Priyadarshini Panda, 2018, ACM J. Emerg. Technol. Comput. Syst..

Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2005, J. Electron. Test..

Impact of body bias on delay fault testing of nanoscale CMOS circuits

Kaushik Roy, Bipul C. Paul, C. Neau, 2004 .

Fault detection and diagnosis using wavelet based transient current analysis

Kaushik Roy, Swarup Bhunia, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering

Kaushik Roy, Chaitali Chakrabarti, Georgios Karakonstantis, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Vertically integrated SOI circuits for low-power and high-performance applications

Kaushik Roy, Liqiong Wei, Rongtian Zhang, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000

Kaushik Roy, Majid Sarrafzadeh, Prithviraj Banerjee, 2000, ACM Great Lakes Symposium on VLSI.

A leakage-tolerant low-leakage register file with conditional sleep transistor

Kaushik Roy, Amit Agarwal, Ram Krishnamurthy, 2004, IEEE International SOC Conference, 2004. Proceedings..

Robust ultra-low power sub-threshold DTMOS logic

Kaushik Roy, Hendrawan Soeleman, Bipul Chandra Paul, 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses

Kaushik Roy, Karthik Yogendra, Deliang Fan, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Modeling, design and cross-layer optimization of polysilicon solar cell based micro-scale energy harvesting systems

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2012, ISLPED '12.

Guest Editors' Introduction: Low-Power VLSI Design

Kaushik Roy, Abhijit Chatterjee, K. Roy, 1994, IEEE Des. Test Comput..

Maximum power estimation for CMOS circuits using deterministic and statistic approaches

Kaushik Roy, Chuan-Yu Wang, 1996, Proceedings of 9th International Conference on VLSI Design.

A novel wavelet transform-based transient current analysis for fault detection and localization

Kaushik Roy, Swarup Bhunia, 2005, IEEE Trans. Very Large Scale Integr. Syst..

Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies

Kaushik Roy, Arijit Raychowdhury, Myeong-Eun Hwang, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency pdf

Kaushik Roy, Indranil Chakraborty, Zubair Al Azim, 2018, ArXiv.

Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

Kaushik Roy, Saibal Mukhopadhyay, Arijit Raychowdhury, 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

Power supply noise aware floorplanning and decoupling capacitance placement

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

HBIST: An approach towards zero external test cost

Kaushik Roy, Ashish Goel, Mayur Bubna, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2005, 14th Asian Test Symposium (ATS'05).

8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing

Kaushik Roy, Indranil Chakraborty, Akhilesh Jaiswal, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits

Kaushik Roy, Chuan-Yu Wang, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2005, J. Electron. Test..

Robust subthreshold logic for ultra-low power operation

Kaushik Roy, Hendrawan Soeleman, Bipul Chandra Paul, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

Mark C. Johnson, Kaushik Roy, Mark Johnson, 1998, ISLPED '98.

Low-Overhead Maximum Power Point Tracking for Micro-Scale Solar Energy Harvesting Systems

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2012, 2012 25th International Conference on VLSI Design.

Test considerations for BiCMOS logic families

Kaushik Roy, M. E. Levitt, Jacob A. Abraham, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ

Kaushik Roy, Vivek De, Ali Keshavarzi, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Convolutional Spike Timing Dependent Plasticity based Feature Learning in Spiking Neural Networks pdf

Kaushik Roy, Gopalakrishnan Srinivasan, Priyadarshini Panda, 2017, ArXiv.

LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family

Kaushik Roy, Dinesh Somasekhar, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Efficient power conversion for ultra low voltage micro scale energy transducers

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

HERQULES: System level cross-layer design exploration for efficient energy-quality trade-offs

Kaushik Roy, Georgios Panagopoulos, Georgios Karakonstantis, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Low-Power Design Techniques and Test Implications

Kaushik Roy, Swarup Bhunia, K. Roy, 2010 .

Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2005, 11th IEEE International On-Line Testing Symposium.

High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM

Kaushik Roy, Xuanyao Fong, Yeongkyo Seo, 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Digital and Analog-Mixed-Signal In-Memory Processing in CMOS SRAM

Kaushik Roy, Indranil Chakraborty, Akhilesh Jaiswal, 2019, ACM Great Lakes Symposium on VLSI.

Exploring SOI device structures and interconnect architectures for 3-dimensional integration

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Enhancing yield at the end of the technology roadmap

Kaushik Roy, Bipul Chandra Paul, Naran Sirisantana, 2004, IEEE Design & Test of Computers.

Voltage over-scaling: A cross-layer design perspective for energy efficient systems

Kaushik Roy, Georgios Karakonstantis, G. Karakonstantis, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

DRG-cache: a data retention gated-ground cache for low power

Kaushik Roy, Amit Agarwal, Hai Li, 2002, DAC '02.

Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons

Kaushik Roy, Shreyas Sen, Priyadarshini Panda, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Process Variations and Process-Tolerant Design

Kaushik Roy, Swarup Bhunia, Saibal Mukhopadhyay, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Low-power carry-select adder using adaptive supply voltage based on input vector patterns

Kaushik Roy, Hiroaki Suzuki, Woopyo Jeong, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

IMPACT: IMPrecise adders for low-power approximate computing

Kaushik Roy, Anand Raghunathan, Vaibhav Gupta, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks

Kaushik Roy, Anand Raghunathan, Deliang Fan, 2014, IEEE Transactions on Nanotechnology.

Control unit synthesis targeting low-power processors

Kaushik Roy, Chuan-Yu Wang, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis

Kaushik Roy, Kunhyuk Kang, Haldun Kufluoglu, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient embedded learning for IoT devices

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Proposal For Neuromorphic Hardware Using Spin Devices pdf

Kaushik Roy, Mrigank Sharad, Charles Augustine, 2012, ArXiv.

POWER ESTIMATION AND SYNTHESIS FOR LOW POWER

Kaushik Roy, 2002 .

Adaptive supply voltage technique for low swing interconnects

Kaushik Roy, Bipul Chandra Paul, Woopyo Jeong, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems

Kaushik Roy, Shreyas Sen, Priyadarshini Panda, 2017, 2017 IEEE International Conference on Rebooting Computing (ICRC).

MACACO: Modeling and analysis of circuits for approximate computing

Kaushik Roy, Amit Agarwal, Anand Raghunathan, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Circuit Optimization by Transistor Reordering for Minimization of Power Consumption under Delay Constraint

Kaushik Roy, Sharat C. Prasad, 1993 .

Controlled Forgetting: Targeted Stimulation and Dopaminergic Plasticity Modulation for Unsupervised Lifelong Learning in Spiking Neural Networks pdf

Kaushik Roy, Jason M. Allred, K. Roy, 2019, Frontiers in Neuroscience.

A process variation aware low power synthesis methodology for fixed-point FIR filters

Kaushik Roy, Nilanjan Banerjee, Jung Hwan Choi, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Peak power reduction in low power BIST

Kaushik Roy, Xiaodong Zhang, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells

Kaushik Roy, Xuanyao Fong, Yusung Kim, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell

Chip-Hong Chang, Kaushik Roy, Xuanyao Fong, 2015, IEEE Transactions on Information Forensics and Security.

Dynamic VTH Scaling Scheme for Active Leakage Power Reduction

Kaushik Roy, Chris H. Kim, 2002, DATE.

Ultra-thin dielectric breakdown in devices and circuits: A brief review

Kaushik Roy, Soo Youn Kim, Chih-Hsiang Ho, 2015, Microelectron. Reliab..

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor

Kaushik Roy, Cheng-Kok Koh, Yiran Chen, 2004 .

A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits

Kaushik Roy, Steven Hsu, Ram Krishnamurthy, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Analysis and characterization of inherent application resilience for approximate computing

Kaushik Roy, Anand Raghunathan, Srimat T. Chakradhar, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

TapeCache: a high density, energy efficient cache based on domain wall memory

Kaushik Roy, Anand Raghunathan, Charles Augustine, 2012, ISLPED '12.

Power Estimation Under Uncertain Delays

Kaushik Roy, Tan-Li Chou, 1998, Integr. Comput. Aided Eng..

Memory design for robust and energy-efficient computing systems

Kaushik Roy, Dongsoo Lee, 2013 .

Spike timing dependent plasticity based enhanced self-learning for efficient pattern recognition in spiking neural networks

Kaushik Roy, Vijay Raghunathan, Gopalakrishnan Srinivasan, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

Maximum power point considerations in micro-scale solar energy harvesting systems

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Unsupervised incremental STDP learning using forced firing of dormant or idle neurons

Kaushik Roy, Jason M. Allred, 2016, 2016 International Joint Conference on Neural Networks (IJCNN).

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2008, J. Electron. Test..

Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, 14th Asian Test Symposium (ATS'05).

Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits

Kaushik Roy, Aditya Bansal, Jayathi Murthy, 2006, ICCAD.

Device/circuit interactions at 22nm technology node

Kaushik Roy, Jaydeep P. Kulkarni, Sumeet Kumar Gupta, 2009, 2009 46th ACM/IEEE Design Automation Conference.

A HighDensity, CarbonNanotube Capacitor forDecoupling Applications

Kaushik Roy, Arijit Raychowdhury, Aditya Bansal, 2006 .

Optimization of Surface Orientation for High-Performance, Low-Power and Robust FinFET SRAM

Kaushik Roy, Saibal Mukhopadhyay, Saakshi Gangwal, 2006, IEEE Custom Integrated Circuits Conference 2006.

Dynamically Resizable Instruction Cache: An Energy-Efficient and High-Performance Deep-Submicron Instruction Cache

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2000 .

Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure

Kaushik Roy, Keith A. Jenkins, Ching-Te Chuang, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Estimation of Maximum Power Spurious for Sequential Circuits Considering Transitions

Kaushik Roy, Chuan-Yu Wang, 1997 .

Exploring Boolean and non-Boolean computing with spin torque devices

Kaushik Roy, Karthik Yogendra, Mrigank Sharad, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A low-power "near-threshold" epileptic seizure detection processor with multiple algorithm programmability

Kaushik Roy, Pedro P. Irazoqui, Shriram Raghunathan, 2012, ISLPED '12.

Ultra-low power DLMS adaptive filter for hearing aid applications

Kaushik Roy, Chris Hyung-Il Kim, 2001, ISLPED '01.

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

Kaushik Roy, Hunsoo Choo, Hamid Mahmoodi, 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Invited — Cross-layer approximations for neuromorphic computing: From devices to circuits and systems

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets

Kaushik Roy, Abhronil Sengupta, Yong Shim, 2015, IEEE Transactions on Biomedical Circuits and Systems.

Viterbi-Based Efficient Test Data Compression

Kaushik Roy, Dongsoo Lee, 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing

Kaushik Roy, Syed Shakib Sarwar, Aayush Ankit, 2017, IEEE Access.

Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Proposal for a Leaky Integrate Fire Spiking Neuron Using Voltage Driven Domain Wall Motion pdf

Kaushik Roy, Akhilesh Jaiswal, Amogh Agrawal, 2017, ArXiv.

Ultra-low Energy, High Performance and Programmable Magnetic Threshold Logic pdf

Kaushik Roy, Mrigank Sharad, Deliang Fan, 2013, ArXiv.

A novel on-chip delay measurement hardware for efficient speed-binning

Kaushik Roy, Swaroop Ghosh, Arijit Raychowdhury, 2005, 11th IEEE International On-Line Testing Symposium.

A high performance IDDQ testable cache for scaled CMOS technologies

Kaushik Roy, Hai Li, Swarup Bhunia, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

Spin Neurons: A Possible Path to Energy-Efficient Neuromorphic Computers pdf

Kaushik Roy, Mrigank Sharad, Deliang Fan, 2013, ArXiv.

Circuit-aware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design

Kaushik Roy, Saibal Mukhopadhyay, Aditya Bansal, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Design of deep sub-micron CMOS circuits

Kaushik Roy, Rajiv V. Joshi, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

On complexity reduction of FIR digital filters using constrained least squares solution

Kaushik Roy, Khurram Muhammad, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

CASh: a novel "Clock As Shield" design methodology for noise immune precharge-evaluate logic

Kaushik Roy, Yonghee Im, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Accelerated BTI degradation under stochastic TDDB effect

Kaushik Roy, Yu Cao, Ethan H. Cannon, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems

Kaushik Roy, Yongtao Wang, K. Roy, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Dynamic bit-width adaptation in DCT

Kaushik Roy, Jongsun Park, Hwan Choi Jung, 2006 .

Adaptive supply voltage technique for low swing interconnects

Kaushik Roy, Bipul C. Paul, Woopyo Jeong, 2004 .

Integer linear programming-based synthesis of skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2003, ASP-DAC '03.

Leakage Current in Deep-Submicron CMOS Circuits

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2002, J. Circuits Syst. Comput..

Designing approximate circuits using clock overgating

Younghoon Kim, Kaushik Roy, Anand Raghunathan, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Exploring SOI device structures and interconnect architecures for 3-dimensional integration

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001, DAC '01.

Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile

Kaushik Roy, Saibal Mukhopadhyay, Arijit Raychowdhury, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters

Kaushik Roy, Nilanjan Banerjee, Jung Hwan Choi, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Cross‐Hierarchy Design Exploration for Implantable Electronics

Kaushik Roy, Mrigank Sharad, M. Sharad, 2014 .

Guest Editorial Computing in Emerging Technologies (Second Issue)

Kaushik Roy, Swarup Bhunia, Saibal Mukhopadhyay, 2015, IEEE J. Emerg. Sel. Topics Circuits Syst..

Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components

Kaushik Roy, Anand Raghunathan, Dimitrios Peroulis, 2010, 2010 23rd International Conference on VLSI Design.

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, Design, Automation and Test in Europe.

Investigation of dependence between time-zero and time-dependent variability in high-κ NMOS transistors

Kaushik Roy, Mohammad Khaled Hassan, 2017, Microelectron. Reliab..

Column-selection-enabled 8T SRAM array with ∼1R/1W multi-port operation for DVFS-enabled processors

Kaushik Roy, Dongsoo Lee, Jae-Joon Kim, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Short-circuit power analysis of an inverter driving an RLC load

Kaushik Roy, Cheng-Kok Koh, Rui Wang, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Noise analysis under capacitive and inductive coupling for high speed circuits

Kaushik Roy, Seung Hoon Choi, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching

Kaushik Roy, Swaroop Ghosh, 2008, 2008 Asia and South Pacific Design Automation Conference.

High performance and low power FIR filter design based on sharing multiplication

Kaushik Roy, Hunsoo Choo, Hamid Mahmoodi, 2002, ISLPED '02.

SAVS: a self-adaptive variable supply-voltage technique for process-tolerant and power-efficient multi-issue superscalar processor design

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Modeling and Analysis of Leakage Currents in Double-Gate Technologies

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multispectral iris recognition based on group selection and game theory

Kaushik Roy, Foysal Ahmad, K. Roy, 2017, Defense + Security.

A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2006, ICCAD.

Coupled Spin-Torque Nano-Oscillator-Based Computation

Kaushik Roy, Karthik Yogendra, Chamika M. Liyanagedera, 2017, ACM J. Emerg. Technol. Comput. Syst..

A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters

Kaushik Roy, Khurram Muhammad, K. Muhammad, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Low-Power and Variation-Tolerant Application-Specific System Design

Kaushik Roy, Georgios Karakonstantis, 2011, Low-Power Variation-Tolerant Design in Nanometer Silicon.

Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost

Kaushik Roy, Ashish Goel, Jeff Parkhurst, 2011, 2011 Asian Test Symposium.

Integrated MEMS Switches for Leakage Control of Battery Operated Systems

Kaushik Roy, Dimitrios Peroulis, Jeong I. Kim, 2006, IEEE Custom Integrated Circuits Conference 2006.

RESPARC: A reconfigurable and energy-efficient architecture with Memristive Crossbars for deep Spiking Neural Networks

Kaushik Roy, Priyadarshini Panda, Abhronil Sengupta, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Energy Efficient and High Performance Current-Mode Neural Network Circuit using Memristors and Digitally Assisted Analog CMOS Neurons pdf

Kaushik Roy, Mrigank Sharad, Siddharth Singh, 2015, ArXiv.

Model reduction in the time-domain using Laguerre polynomials and Krylov methods

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Estimation of circuit activity considering signal correlations and simultaneous switching

Kaushik Roy, Tan-Li Chou, Sharat Prasad, 1994, ICCAD '94.

Optimal selection of supply voltages and level conversions during data path scheduling under resource constraints

Mark C. Johnson, Kaushik Roy, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and its Application to Digital Signal Processing Systems

Kaushik Roy, Charles Augustine, Nilanjan Banerjee, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

Low-Power and testable circuit synthesis using Shannon decomposition

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2007, TODE.

Low voltage low power CMOS design techniques for deep submicron ICs

Kaushik Roy, Vivek De, Liqiong Wei, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd

Kaushik Roy, Swaroop Ghosh, Pooja Batra, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Device optimization for ultra-low power digital sub-threshold operation

Kaushik Roy, Arijit Raychowdhury, Bipul Chandra Paul, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

A new crosstalk noise model for DOMINO logic circuits

Kaushik Roy, Seung Hoon Choi, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Tutorial: SoC Power Management Verification and Testing Issues

Kaushik Roy, Bhanu Kapoor, Shireesh Verma, 2008, 2008 Ninth International Workshop on Microprocessor Test and Verification.

A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An All-Memristor Deep Spiking Neural Network: A Step Towards Realizing the Low Power, Stochastic Brain pdf

Kaushik Roy, Parami Wijesinghe, Abhronil Sengupta, 2017, ArXiv.

Technology and Circuit Design Considerations in

Kaushik Roy, Hari Ananthan, 2006 .

Modeling of ballistic carbon nanotube field effect transistors for efficient circuit simulation

Kaushik Roy, Saibal Mukhopadhyay, Arijit Raychowdhury, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

I/sub DD/ waveforms analysis for testing of domino and low voltage static CMOS circuits

Kaushik Roy, Hendrawan Soeleman, Dinesh Somasekhar, 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture

Kaushik Roy, Anand Raghunathan, Sumeet Kumar Gupta, 2012, DAC Design Automation Conference 2012.

A high sensitivity process variation sensor utilizing sub-threshold operation

Kaushik Roy, Franco Stellari, Peilin Song, 2008, 2008 IEEE Custom Integrated Circuits Conference.

Verifying Reliability (Dagstuhl Seminar 12341)

Kaushik Roy, Masahiro Fujita, Görschwin Fey, 2012, Dagstuhl Reports.

Ultra low power associative computing with spin neurons and resistive crossbar memory

Kaushik Roy, Mrigank Sharad, Deliang Fan, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Low-power design techniques for scaled technologies

Kaushik Roy, Amit Agarwal, Bipul Chandra Paul, 2006, Integr..

Impact of body bias on delay fault testing of nanoscale CMOS circuits

Kaushik Roy, Bipul Chandra Paul, Cassondra Neau, 2004, 2004 International Conferce on Test.

Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders

Kaushik Roy, Hiroaki Suzuki, Woopyo Jeong, 2007, IEICE Trans. Electron..

Sub-10 nm FinFETs and tunnel-FETs: From devices to systems

Kaushik Roy, Ankit Sharma, A. Arun Goud, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Performance analysis and benchmarking of all-spin spiking neural networks (Special session paper)

Kaushik Roy, Abhronil Sengupta, Aayush Ankit, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

Approximate computing: enabling voltage over-scaling in multimedia applications

Kaushik Roy, Debabrata Mohapatra, 2011 .

Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2007 .

ReStoCNet: Residual Stochastic Binary Convolutional Spiking Neural Network for Memory-Efficient Neuromorphic Computing

Kaushik Roy, Gopalakrishnan Srinivasan, K. Roy, 2019, Front. Neurosci..

RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient Neural Computing

Kaushik Roy, Amogh Agrawal, 2018, 2018 IEEE International Workshop on Signal Processing Systems (SiPS).

Spin-Torque Sensors for Energy Efficient High-Speed Long Interconnects

Kaushik Roy, Syed Shakib Sarwar, Abhronil Sengupta, 2015, IEEE Transactions on Electron Devices.

CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multiple-parameter CMOS IC testing with increased sensitivity for I/sub DDQ/

Kaushik Roy, Vivek De, Ali Keshavarzi, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Transistor reordering for power minimization under delay constraint

Kaushik Roy, S. C. Prasad, 1996, TODE.

Adaptive accelerated aging for 28 nm HKMG technology

Kaushik Roy, Yu Cao, Ethan H. Cannon, 2018, Microelectron. Reliab..

A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption

Kaushik Roy, Jongsun Park, K. Roy, 2008, J. Signal Process. Syst..

An XOR-Based Decomposition Diagram and Its Application in Synthesis of AND/XOR Networks (Special Section on VLSI Design and CAD Algorithms)

Kaushik Roy, Yibin Ye, 1997 .

Design of a Low-Voltage Analog-to-Digital Converter Using Voltage-Controlled Stochastic Switching of Low Barrier Nanomagnets

Kaushik Roy, Indranil Chakraborty, Amogh Agrawal, 2018, IEEE Magnetics Letters.

A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

Kaushik Roy, Chris H. Kim, Saibal Mukhopadhyay, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area

Kaushik Roy, Aditya Bansal, Dheepa Lekshmanan, 2007, 2007 IEEE Custom Integrated Circuits Conference.

A graph-based synthesis algorithm for AND/XOR networks

Kaushik Roy, Yibin Ye, 1997, DAC.

STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

On Modeling and Evaluation of Logic Circuits under Timing Variations

Kaushik Roy, Anand Raghunathan, Görschwin Fey, 2012, 2012 15th Euromicro Conference on Digital System Design.

Quality programmable vector processors for approximate computing

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

BiCMOS logic testing

Kaushik Roy, Jacob A. Abraham, Marc E. Levitt, 1994, IEEE Trans. Very Large Scale Integr. Syst..

DyReCTape: A dynamically reconfigurable cache using domain wall memory tapes

Kaushik Roy, Anand Raghunathan, Ashish Ranjan, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Magnetic Tunnel Junction Enabled Stochastic Spiking Neural Networks: From Non-Telegraphic to Telegraphic Switching Regime pdf

Kaushik Roy, Chamika M. Liyanagedera, Abhronil Sengupta, 2017, ArXiv.

A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS

Kaushik Roy, Jae-Joon Kim, Ik Joon Chang, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Low power design under parameter variations

Kaushik Roy, Swarup Bhunia, 2008, SoCC.

Hardware-Software Co-Design for an Analog-Digital Accelerator for Machine Learning

Dejan S. Milojicic, Kaushik Roy, Paolo Faraboschi, 2018, 2018 IEEE International Conference on Rebooting Computing (ICRC).

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM

Kaushik Roy, Jaydeep P. Kulkarni, Keejong Kim, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Leakage control with efficient use of transistor stacks in single threshold CMOS

Mark C. Johnson, Kaushik Roy, Dinesh Somasekhar, 1999, DAC '99.

Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons

Kaushik Roy, Parami Wijesinghe, Priyadarshini Panda, 2015, Scientific Reports.

Spintronic devices for ultra-low power neuromorphic computation (Special session paper)

Kaushik Roy, Karthik Yogendra, Abhronil Sengupta, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Maximization of power dissipation in large CMOS circuits considering spurious transitions

Kaushik Roy, Chun-yao Wang, 2000 .

VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power

Kaushik Roy, Hai Li, Chen-Yong Cher, 2003, MICRO.

SPARE: Spiking Neural Network Acceleration Using ROM-Embedded RAMs as In-Memory-Computation Primitives

Kaushik Roy, Amogh Agrawal, Aayush Ankit, 2017, IEEE Transactions on Computers.

CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations

Kaushik Roy, Anand Raghunathan, W. Paul Griffin, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits

Kaushik Roy, David Bol, François Botman, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low-power approximate convolution computing unit with domain-wall motion based “Spin-Memristor” for image processing applications

Kaushik Roy, Abhronil Sengupta, Yong Shim, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Multiple-V/sub dd/ scheduling/allocation for partitioned floorplan

Mark C. Johnson, Kaushik Roy, Dongku Kang, 2003, Proceedings 21st International Conference on Computer Design.

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation

Kaushik Roy, Seong-Ook Jung, Myeong-Eun Hwang, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

A novel approach to high-level switching activity modeling with applications to low-power DSP system synthesis

Kaushik Roy, Khurram Muhammad, Sarah Kate Wilson, 2001, IEEE Trans. Signal Process..

ASLAN: Synthesis of approximate sequential circuits

Kaushik Roy, Anand Raghunathan, Arnab Raha, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A fully physical model for leakage distribution under process variations in nanoscale double-gate CMOS

Kaushik Roy, Hari Ananthan, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Estimation of average switching power under accurate modeling of signal correlations

Kaushik Roy, Zhanping Chen, Yibin Ye, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology

Kaushik Roy, Farshad Moradi, Hamid Mahmoodi, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Performance and Wirability Driven Layout for Row-Based FPGAs

Kaushik Roy, Sudip Nag, K. Roy, 1998, VLSI Design.

A twisted-bundle layout structure for minimizing inductive coupling noise

Kaushik Roy, Cheng-Kok Koh, Guoan Zhong, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

On effective I/sub DDQ/ testing of low voltage CMOS circuits using leakage control techniques

Kaushik Roy, Liqiong Wei, Zhanping Chen, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies

Kaushik Roy, Mark M. Budnik, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On-chip interconnect modeling by wire duplication

Kaushik Roy, Cheng-Kok Koh, Guoan Zhong, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Low Power Design Methodologies for Systems-on-Chips

Kaushik Roy, Sujit Dey, Anand Raghunathan, 1999, VLSI Design.

A novel design methodology for high performance and low power digital filters

Kaushik Roy, Khurram Muhammad, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency

Kaushik Roy, Anand Raghunathan, Srimat T. Chakradhar, 2010, Design Automation Conference.

A coarse-grained FPGA architecture for high-performance FIR filtering

Kaushik Roy, James R. Anderson, Siddharth Sheth, 1998, FPGA '98.

An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function

Kaushik Roy, Arjun Guha, Qikai Chen, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Semantic driven hierarchical learning for energy-efficient image classification

Kaushik Roy, Priyadarshini Panda, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

First level hold: a novel low-overhead delay fault testing technique

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2004 .

Selectively clocked CMOS logic style for low-power noise-immune operations in scaled technologies

Kaushik Roy, Naran Sirisantana, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Ising spin model using Spin-Hall Effect (SHE) induced magnetization reversal in Magnetic-Tunnel-Junction pdf

Kaushik Roy, Akhilesh Jaiswal, Yong Shim, 2016, ArXiv.

Robust Level Converter Design for Sub-threshold Logic

Kaushik Roy, Jae-Joon Kim, Ik Joon Chang, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Approximate computing for efficient information processing

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2014, 2014 IEEE 12th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia).

A novel wavelet transform-based transient current analysis for fault detection and localization

Kaushik Roy, Swarup Bhunia, Jaume Segura, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars

Kaushik Roy, Anand Raghunathan, Shubham Jain, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A high density, carbon nanotube capacitor for decoupling applications

Kaushik Roy, Arijit Raychowdhury, Aditya Bansal, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ

Kaushik Roy, Kunhyuk Kang, Muhammad Ashraful Alam, 2007, 2007 IEEE International Test Conference.

Energy efficient computing using coupled Dual-Pillar Spin Torque Nano Oscillators

Kaushik Roy, Karthik Yogendra, Mrigank Sharad, 2013, 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching

Kaushik Roy, Florentin Dartu, Kunhyuk Kang, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Simultaneous multiple-V/sub dd/ scheduling and allocation for partitioned floorplan

Mark C. Johnson, Kaushik Roy, Dongku Kang, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Magnetic tunnel junction enabled all-spin stochastic spiking neural network

Kaushik Roy, Gopalakrishnan Srinivasan, Abhronil Sengupta, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Energy recovery clocked dynamic logic

Kaushik Roy, Hamid Mahmoodi, Matthew Cooke, 2005, GLSVLSI '05.

Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays

Kaushik Roy, Chao Lu, Debabrata Mohapatra, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2000, ISLPED '00.

Novel low-overhead operand isolation techniques for low-power datapath synthesis

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, 2005 International Conference on Computer Design.

High level test generation using data flow descriptions

Kaushik Roy, Jacob A. Abraham, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, IEEE International Conference on Test, 2005..

Approximate computing: Energy-efficient computing with good-enough results

Kaushik Roy, Anand Raghunathan, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures

Kaushik Roy, Sang Phill Park, Kunhyuk Kang, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Synthesis of delay fault testable combinational logic

Kaushik Roy, Jacob A. Abraham, Kaushik De, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Domain wall motion-based low power hybrid spin-CMOS 5-bit Flash Analog Data Converter

Kaushik Roy, Karthik Yogendra, Xuanyao Fong, 2015, Sixteenth International Symposium on Quality Electronic Design.

On-chip interconnect modeling by wire duplication

Kaushik Roy, Cheng-Kok Koh, Guoan Zhong, 2002, ICCAD 2002.

Dynamically Resizable Instruction Cache: A Design for an Energy-Efficient and High-Performance Deep-Submicron Instruction Cache

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2000 .

Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches

Kaushik Roy, Anand Raghunathan, Xuanyao Fong, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs

Kaushik Roy, Jing Li, Swaroop Ghosh, 2007, 2007 IEEE International Test Conference.

Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability

Kaushik Roy, Ashish Goel, Swarup Bhunia, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization

Kaushik Roy, Akhilesh Jaiswal, Yong Shim, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Variation-tolerant Spin-Torque Transfer (STT) MRAM array for yield enhancement

Kaushik Roy, Jing Li, Haixin Liu, 2008, 2008 IEEE Custom Integrated Circuits Conference.

A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues

Kaushik Roy, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Analysis and design of ultra low power thermoelectric energy harvesting systems

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Test consideration for nanometer-scale CMOS circuits

Kaushik Roy, Kwang-Ting Cheng, T. M. Mak, 2006, IEEE Design & Test of Computers.

Probabilistic Deep Spiking Neural Systems Enabled by Magnetic Tunnel Junction

Kaushik Roy, Bing Han, Abhronil Sengupta, 2016, IEEE Transactions on Electron Devices.

Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches

Kaushik Roy, Anand Raghunathan, Mrigank Sharad, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Poly-Si Thin Film Transistors: Opportunities for low-cost RF applications

Kaushik Roy, Byunghoo Jung, Sang Phill Park, 2012, 2012 IEEE International Conference on IC Design & Technology.

I/sub DDQ/ testing for deep-submicron ICs: challenges and solutions

Kaushik Roy, Ali Keshavarzi, Liqiong Wei, 2002, IEEE Design & Test of Computers.

Leakage and process variation effects in current testing on future CMOS circuits

Kaushik Roy, James Tschanz, Vivek De, 2002, IEEE Design & Test of Computers.

Spin Orbit Torque Based Electronic Neuron pdf

Kaushik Roy, Abhronil Sengupta, Yusung Kim, 2014, ArXiv.

Intrinsic leakage in low power deep submicron CMOS ICs

Kaushik Roy, Ali Keshavarzi, Charles F. Hawkins, 1997, Proceedings International Test Conference 1997.

Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths

Kaushik Roy, Swaroop Ghosh, Patrick Ndai, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Spin transfer torque memories for on-chip caches: Prospects and perspectives

Kaushik Roy, Akhilesh Jaiswal, 2016, 2016 17th Latin-American Test Symposium (LATS).

Reducing set-associative cache energy via way-prediction and selective direct-mapping

Kaushik Roy, Amit Agarwal, Babak Falsafi, 2001, MICRO.

Image segmentation with stochastic magnetic tunnel junctions and spiking neurons

Kaushik Roy, Parami Wijesinghe, Chamika M. Liyanagedera, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

Testing cross-talk induced delay faults in static CMOS circuit through dynamic timing analysis

Kaushik Roy, Bipul Chandra Paul, 2002, Proceedings. International Test Conference.

A novel synthesis approach for active leakage power reduction using dynamic supply gating

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, Proceedings. 42nd Design Automation Conference, 2005..

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Robust and high sensitivity biosensor using injection locked spin torque nano-oscillators

Kaushik Roy, Mrigank Sharad, Anand Kumar Mukhopadhyay, 2016, 2016 74th Annual Device Research Conference (DRC).

Guest Editorial

Kaushik Roy, 2006, Integr..

Low-power weighted random pattern testing

Kaushik Roy, Xiaodong Zhang, Wenlei Shan, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An efficient statistical method to estimate average power in sequential circuits considering input sensitivities

Kaushik Roy, Zhanping Chen, 1997, Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334).

A novel bitstream level joint channel error concealment scheme for realtime video over wireless networks

Kaushik Roy, Xiaowei Ding, 2004, IEEE INFOCOM 2004.

Timed pattern generation for noise-on-delay calculation

Kaushik Roy, Florentin Dartu, Seung Hoon Choi, 2002, DAC '02.

Scalable Effort Hardware Design

Kaushik Roy, Anand Raghunathan, Srimat T. Chakradhar, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2005, 14th Asian Test Symposium (ATS'05).

Scaled LTPS TFTs for low-cost low-power applications

Kaushik Roy, Soo Youn Kim, Selin Baytok, 2011, 2011 12th International Symposium on Quality Electronic Design.

M2CA: Modular Memristive Crossbar Arrays

Kaushik Roy, Alex Pappachen James, Chamika M. Liyanagedera, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

Kaushik Roy, Mrigank Sharad, Deliang Fan, 2014, IEEE Transactions on Nanotechnology.

Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Statistical design and optimization of SRAM cell for yield enhancement

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2004, ICCAD 2004.

SYCLOP: synthesis of CMOS logic for low power applications

Kaushik Roy, Sharat Prasad, S. Prasad, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Power consumption in XOR-based circuits

Rolf Drechsler, Kaushik Roy, Yibin Ye, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Joint control of communication subsystems for low-energy image transmission

Kaushik Roy, Hunsoo Choo, 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..

Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications

Kaushik Roy, Jing Li, Kunhyuk Kang, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Low-power design using multiple channel lengths and oxide thicknesses

Kaushik Roy, Naran Sirisantana, 2004, IEEE Design & Test of Computers.

An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor

Suku Nair, Kaushik Roy, Jacob A. Abraham, 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

FinFET Based SRAM Design for Low Standby Power Applications

Kaushik Roy, Keejong Kim, Tamer Cakici, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Dynamic noise analysis in precharge-evaluate circuits

Kaushik Roy, Vivek De, Dinesh Somasekhar, 2000, Proceedings 37th Design Automation Conference.

PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices

Kaushik Roy, Charles Augustine, Arijit Raychowdhury, 2009, 2009 10th International Symposium on Quality Electronic Design.

Exploring high bandwidth pipelined cache architecture for scaled technology

Kaushik Roy, Amit Agarwal, T. N. Vijaykumar, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Timed Pattern Generation for

Kaushik Roy, Seunq Hoon Choi, 2002 .

Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator

Kaushik Roy, Georgios Karakonstantis, Debabrata Mohapatra, 2009, ISLPED.

Exploiting Inherent Error-Resiliency of Neuromorphic Computing to achieve Extreme Energy-Efficiency through Mixed-Signal Neurons pdf

Kaushik Roy, Shreyas Sen, Priyadarshini Panda, 2018, ArXiv.

Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology

Kaushik Roy, T. N. Vijaykumar, Amit Agarwal, 2003, Embedded Software for SoC.

Frequency specification testing of analog filters using wavelet transform of dynamic supply current

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

Kaushik Roy, Santanu Dutta, Sudip Nag, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Quasi-static energy recovery logic and supply-clock generation circuits

Kaushik Roy, Yibin Ye, Georgios I. Stamoulis, 1997, ISLPED '97.

Switching characteristics of generalized array multiplier architectures and their applications to low power design

Kaushik Roy, Khurram Muhammad, Dinesh Somasekhar, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Gate leakage reduction for scaled devices using transistor stacking

Kaushik Roy, Amit Agarwal, Chris H. Kim, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation

Kaushik Roy, Saibal Mukhopadhyay, 2003, ISLPED '03.

Minimally redundant parallel implementation of digital filters and vector scaling

Kaushik Roy, Khurram Muhammad, 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).

Technology Aware Training in Memristive Neuromorphic Systems based on non-ideal Synaptic Crossbars pdf

Kaushik Roy, Indranil Chakraborty, Deboleena Roy, 2017, ArXiv.

Models and algorithms for bounds on leakage in CMOS circuits

Mark C. Johnson, Kaushik Roy, Dinesh Somasekhar, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Energy efficient many-core processor for recognition and mining using spin-based memory

Kaushik Roy, Anand Raghunathan, Charles Augustine, 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

A novel low-complexity method for parallel multiplierless implementation of digital FIR filters

Kaushik Roy, Yongtao Wang, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Device-Aware Yield-Centric Dual-$V_{t}$ Design Under Parameter Variations in Nanoscale Technologies

Kaushik Roy, Amit Agarwal, Swarup Bhunia, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors

Kaushik Roy, Hiroaki Suzuki, Chris H. Kim, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

On The Design of Adiabatic SRAMs

Kaushik Roy, Yibin Ye, Dinesh Somasekhar, 1996 .

Power Dissipation Driven FPGA Place and Route Under Delay Constraints

Kaushik Roy, Sharat Prasad, 1994, FPL.

Self calibrating circuit design for variation tolerant VLSI systems

Kaushik Roy, Steven Hsu, Ram Krishnamurthy, 2005, 11th IEEE International On-Line Testing Symposium.

O2ABA: a novel high-performance predictable circuit architecture for the deep submicron era

Kaushik Roy, Yonghee Im, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Combined circuit and architectural level variable supply-voltage scaling for low power

Kaushik Roy, Hai Li, Chen-Yong Cher, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of voltage-scalable meta-functions for approximate computing

Kaushik Roy, Anand Raghunathan, Debabrata Mohapatra, 2011, 2011 Design, Automation & Test in Europe.

Enabling Spike-Based Backpropagation for Training Deep Neural Network Architectures

Kaushik Roy, Chankyu Lee, Syed Shakib Sarwar, 2019, Frontiers in Neuroscience.

Chaos-guided Input Structuring for Improved Learning in Recurrent Neural Networks pdf

Kaushik Roy, Priyadarshini Panda, K. Roy, 2017, ArXiv.

TFT-LCD application specific low power SRAM using charge-recycling technique

Kaushik Roy, Chris H. Kim, Keejong Kim, 2005, Sixth international symposium on quality electronic design (isqed'05).

Spin based neuron-synapse module for ultra low power programmable computational networks

Kaushik Roy, Mrigank Sharad, Charles Augustine, 2012, The 2012 International Joint Conference on Neural Networks (IJCNN).

MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic

Kaushik Roy, Akhilesh Jaiswal, K. Roy, 2016, Scientific Reports.

Optimizing computations in a transposed direct form realization of Floating-Point LTI-FIR systems

Kaushik Roy, Debashis Bhattacharya, Naushik Sankarayya, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

A low power reconfigurable DCT architecture to trade off image quality for computational complexity

Kaushik Roy, Jongsun Park, 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

A 135mV 0.13μW process tolerant 6T subthreshold DTMOS SRAM in 90nm technology

Kaushik Roy, Myeong-Eun Hwang, K. Roy, 2008, 2008 IEEE Custom Integrated Circuits Conference.

Estimation of maximum power for sequential circuits considering spurious transitions

Kaushik Roy, Chuan-Yu Wang, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array

Kaushik Roy, Patrick Ndai, Ashish Goel, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A novel low-power scan design technique using supply gating

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions

Kaushik Roy, Swarup Bhunia, K. Roy, 2007, 2007 IEEE International Test Conference.

Accurate Power Estimation of Combinational CMOS Digital Circuits

Kaushik Roy, Hendrawan Soeleman, 2017 .

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors

Kaushik Roy, Patrick Ndai, Ashish Goel, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Datapath scheduling with multiple supply voltages and level converters

Mark C. Johnson, Kaushik Roy, K. Roy, 1997, TODE.

Dynamic noise analysis with capacitive and inductive coupling [high-speed circuits]

Kaushik Roy, Bipul Chandra Paul, Seung Hoon Choi, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Delay fault localization in test-per-scan BIST using built-in delay sensor

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

Leakage Power Analysis and Reduction for Nanoscale Circuits

Kaushik Roy, Amit Agarwal, Chris H. Kim, 2006, IEEE Micro.

Low-power process-variation tolerant arithmetic units using input-based elastic clocking

Kaushik Roy, Georgios Karakonstantis, Debabrata Mohapatra, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Unsupervised regenerative learning of hierarchical features in Spiking Deep Networks for object recognition

Kaushik Roy, Priyadarshini Panda, K. Roy, 2016, 2016 International Joint Conference on Neural Networks (IJCNN).

Synthesis of application-specific highly-efficient multi-mode systems for low-power applications

Kaushik Roy, Swarup Bhunia, Lih-Yih Chiou, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits

Kaushik Roy, Rajiv V. Joshi, Ching-Te Chuang, 2005, Sixth international symposium on quality electronic design (isqed'05).

A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking

Kaushik Roy, Swaroop Ghosh, Patrick Ndai, 2008, 2008 Design, Automation and Test in Europe.

Dual pillar spin-transfer torque MRAMs for low power applications

Kaushik Roy, Xuanyao Fong, Charles Augustine, 2013, JETC.

Design and optimization of double-gate SOI MOSFETs for low voltage low power circuits

Kaushik Roy, Liqiong Wei, Z. Chen, 1998, 1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199).

Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications

Kaushik Roy, Khurram Muhammad, Lih-Yih Chiou, 2001, VLSI Design.

Process Variation Tolerant Low Power DCT Architecture

Kaushik Roy, Georgios Karakonstantis, Nilanjan Banerjee, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Low-power driven logic synthesis using accurate power estimation technique

Kaushik Roy, Tan-Li Chou, R. Roy, 1997, Proceedings Tenth International Conference on VLSI Design.

Workload dependent evaluation of thin-film thermoelectric devices for on-chip cooling and energy harvesting

Kaushik Roy, Kon-Woo Kwon, Sri Harsha Choday, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

First level hold: a novel low-overhead delay fault testing technique

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

Design verification and robust design technique for cross-talk faults

Kaushik Roy, Bipul Chandra Paul, Yonghee Im, 2001, Proceedings 10th Asian Test Symposium.

Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation

Kaushik Roy, Ik Joon Chang, Sang Phill Park, 2010, IEEE Journal of Solid-State Circuits.

PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference

Dejan S. Milojicic, Kaushik Roy, Paolo Faraboschi, 2019, ASPLOS.

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited

Kaushik Roy, Anand Raghunathan, Sachin S. Sapatnekar, 2017, DAC.

Analysis of Super Cut-off Transistors for Ultralow Power Digital Logic Circuits

Kaushik Roy, Xuanyao Fong, Arijit Raychowdhury, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Spintastic: Spin-based stochastic logic for energy-efficient computing

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Design of ultra high density and low power computational blocks using nano-magnets

Kaushik Roy, Karthik Yogendra, Mrigank Sharad, 2013, International Symposium on Quality Electronic Design (ISQED).

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM

Kaushik Roy, Swaroop Ghosh, Saibal Mukhopadhyay, 2006, 2006 43rd ACM/IEEE Design Automation Conference.

Ultra-low Energy, High-Performance Dynamic Resistive Threshold Logic pdf

Kaushik Roy, Mrigank Sharad, Deliang Fan, 2013, ArXiv.

On the energy benefits of spiking deep neural networks: A case study

Kaushik Roy, Bing Han, Abhronil Sengupta, 2016, 2016 International Joint Conference on Neural Networks (IJCNN).

Layout-driven architecture synthesis for high-speed digital filters

Kaushik Roy, Hunsoo Choo, Khurram Muhammad, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Synthesis of application-specific highly efficient multi-mode cores for embedded systems

Kaushik Roy, Swarup Bhunia, Lih-Yih Chiou, 2005, TECS.

A power-aware GALS architecture for real-time algorithm-specific tasks

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2005, Sixth international symposium on quality electronic design (isqed'05).

Non-adaptive and adaptive filter implementation based on sharing multiplication

Kaushik Roy, Hunsoo Choo, Khurram Muhammad, 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).

Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars pdf

Kaushik Roy, Anand Raghunathan, Shubham Jain, 2018, ArXiv.

Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components

Kaushik Roy, Anand Raghunathan, Byunghoo Jung, 2010, IEEE Design & Test.

Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking

Kaushik Roy, Swaroop Ghosh, K. Roy, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Evaluating Opportunity and Effectiveness of Cache Resizing in Reducing Energy Dissipation

Kaushik Roy, T. N. Vijaykumar, Se-Hyun Yang, 2001 .

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

Kaushik Roy, Jaydeep P. Kulkarni, K. Roy, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Leakage in nano-scale technologies: mechanisms, impact and design considerations

Kaushik Roy, Amit Agarwal, Chris H. Kim, 2004, Proceedings. 41st Design Automation Conference, 2004..

A metric for analyzing effective on-chip inductive coupling

Kaushik Roy, Cheng-Kok Koh, Guoan Zhong, 2003, ASP-DAC '03.

Asymmetric underlapped FinFET based robust SRAM design at 7nm node

Kaushik Roy, Anand Raghunathan, Rangharajan Venkatesan, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Object Detection using Semantic Decomposition for Energy-Efficient Neural Computing pdf

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2015, ArXiv.

A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies

Kaushik Roy, Arijit Raychowdhury, K. Roy, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

EnsembleSNN: Distributed assistive STDP learning for energy-efficient recognition in spiking neural networks

Kaushik Roy, Gopalakrishnan Srinivasan, Priyadarshini Panda, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling

Kaushik Roy, Myeong-Eun Hwang, K. Roy, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Logic synthesis for reliability—an early start to controlling electromigration and hot carrier effects

Kaushik Roy, Sharat Prasad, 1994, EURO-DAC '94.

Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's

Kaushik Roy, Vivek De, Shekhar Y. Borkar, 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance

Kaushik Roy, Sang Phill Park, Kunhyuk Kang, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

DCG: deterministic clock-gating for low-power microprocessor design

Yiran Chen, Kaushik Roy, Swarup Bhunia, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Computing with Spin-Transfer-Torque Devices: Prospects and Perspectives

Kaushik Roy, Karthik Yogendra, Mrigank Sharad, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Trim bit setting of analog filters using wavelet-based supply current analysis

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop

Kaushik Roy, Kunhyuk Kang, Keejong Kim, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Design and optimization of dual-threshold circuits for low-voltage low-power applications

Mark C. Johnson, Kaushik Roy, Vivek De, 1999, IEEE Trans. Very Large Scale Integr. Syst..

Conditional Deep Learning for energy-efficient and enhanced pattern recognition

Kaushik Roy, Priyadarshini Panda, Abhronil Sengupta, 2015, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices

Kaushik Roy, Rajiv V. Joshi, Ching-Te Chuang, 2007, Microelectron. J..

A Novel Delay Fault Testing Methodology Using On-chip Low-overhead Delay Measurement Hardware at Strategic Probe Points

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2005 .

Low-power design

Kaushik Roy, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling

Kaushik Roy, Jongsun Park, Ik Joon Chang, 2010, IET Circuits Devices Syst..

A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique

Kaushik Roy, Charles Augustine, Georgios Karakonstantis, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

CSDC: a new complexity reduction technique for multiplierless implementation of digital FIR filters

Kaushik Roy, Yongtao Wang, K. Roy, 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

Micro-scale energy harvesting: A system design perspective

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

All-Photonic Phase Change Spiking Neuron: Toward Fast Neural Computing using Light pdf

Kaushik Roy, Indranil Chakraborty, Gobinda Saha, 2018, ArXiv.

Speed binning aware design methodology to improve profit under parameter variations

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2006, Asia and South Pacific Conference on Design Automation, 2006..

An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping

Kaushik Roy, Bipul Chandra Paul, Aditya Bansal, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems pdf

Kaushik Roy, Abhronil Sengupta, Aparajita Banerjee, 2015, ArXiv.

Synthesis of skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2005, TODE.

A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors

Kaushik Roy, Debabrata Mohapatra, Ik Joon Chang, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Thermal analysis of 8-T SRAM for nano-scaled technologies

Kaushik Roy, Jaydeep P. Kulkarni, Mesut Meterelliyoz, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness

Kaushik Roy, Liqiong Wei, Naran Sirisantana, 2000, Proceedings 2000 International Conference on Computer Design.

Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology

Kaushik Roy, Siddharth Singh, Aditya Bansal, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Kaushik Roy, Farshad Moradi, Hamid Mahmoodi, 2014, Microelectron. J..

Statistical estimation of combinational and sequential CMOS digital circuit activity considering uncertainty of gate delays

Kaushik Roy, Tan-Li Chou, T. Chou, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Reducing set-associative cache energy via way-prediction and selective direct-mapping

Kaushik Roy, T. N. Vijaykumar, Amit Agarwal, 2001, Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34.

Multiple-parameter side-channel analysis: A non-invasive hardware Trojan detection approach

Kaushik Roy, Christos A. Papachristou, Francis G. Wolff, 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

A leakage control system for thermal stability during burn-in test

Kaushik Roy, Hamid Mahmoodi, Mesut Meterelliyoz, 2005, IEEE International Conference on Test, 2005..

Digital LDO with Time-Interleaved Comparators for Fast Response and Low Ripple

Kaushik Roy, Mrigank Sharad, Sohail Ahasan, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions

Kaushik Roy, Ali Keshavarzi, Charles F. Hawkins, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Attention Tree: Learning Hierarchies of Visual Features for Large-Scale Image Recognition pdf

Kaushik Roy, Priyadarshini Panda, K. Roy, 2016, ArXiv.

TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design

Kaushik Roy, Abhronil Sengupta, Aayush Ankit, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Approximate Computing

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors

Kaushik Roy, Swaroop Ghosh, Patrick Ndai, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Spin-Orbit Torque Induced Spike-Timing Dependent Plasticity pdf

Kaushik Roy, Xuanyao Fong, Abhronil Sengupta, 2014, ArXiv.

Powerline Communication for Enhanced Connectivity in Neuromorphic Systems

Kaushik Roy, Shreyas Sen, Minsuk Koo, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Network-based simulation laboratories for microelectronics systems design and education

Kaushik Roy, José A. B. Fortes, Nirav H. Kapadia, 1997, Proceedings of International Conference on Microelectronic Systems Education.

Leakage grading of inputs to CMOS logic

Kaushik Roy, Dinesh Somasekhar, Mark C. Johnson, 1998 .

Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era

Kaushik Roy, Swaroop Ghosh, K. Roy, 2010, Proceedings of the IEEE.

Process variation in nano-scale memories: failure analysis and process tolerant architecture

Kaushik Roy, Amit Agarwal, Bipul Chandra Paul, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

REDUCING GLITCHING AND LEAKAGE POWER IN LOW VOLTAGE CMOS CIRCUITS

Kaushik Roy, Liqiong Wei, Zhanping Chen, 1997 .

Energy-Efficient Memory Using Magneto-Electric Switching of Ferromagnets

Kaushik Roy, Indranil Chakraborty, Akhilesh Jaiswal, 2017, IEEE Magnetics Letters.

Dynamic effort scaling: Managing the quality-efficiency tradeoff

Kaushik Roy, Anand Raghunathan, Srimat T. Chakradhar, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering

Kaushik Roy, Hunsoo Choo, Hamid Mahmoodi, 2010, J. Signal Process. Syst..

SPINDLE: SPINtronic Deep Learning Engine for large-scale neuromorphic computing

Kaushik Roy, Anand Raghunathan, Mrigank Sharad, 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Design and Test of Low Voltage CMOS Circuits

Kaushik Roy, Ali Keshavarzi, 2001, ISQED.

Optimal body bias selection for leakage improvement and process compensation over different technology generations

Kaushik Roy, Cassondra Neau, 2003, ISLPED '03.

Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, IEEE Journal of Solid-State Circuits.

STAxCache: An approximate, energy efficient STT-MRAM cache

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2005, ISQED.

A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach

Kaushik Roy, Charles Augustine, Georgios Panagopoulos, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A process-tolerant cache architecture for improved yield in nanoscale technologies

Kaushik Roy, Amit Agarwal, Animesh Datta, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low-Power Digital Signal Processing Using Approximate Adders

Kaushik Roy, Anand Raghunathan, Vaibhav Gupta, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Novel sizing algorithm for yield improvement under process variation in nanometer technology

Kaushik Roy, Bipul Chandra Paul, Seung Hoon Choi, 2004, Proceedings. 41st Design Automation Conference, 2004..

A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime

Kaushik Roy, Amit Agarwal, A. Agarwal, 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

Process variation tolerant online current monitor for robust systems

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, 11th IEEE International On-Line Testing Symposium.

Area Efficient ROM-Embedded SRAM Cache

Kaushik Roy, Dongsoo Lee, K. Roy, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage

Kaushik Roy, Anand Raghunathan, Mrigank Sharad, 2015, ACM J. Emerg. Technol. Comput. Syst..

Staged Inference using Conditional Deep Learning for energy efficient real-time smart diagnosis

Kaushik Roy, Shreyas Sen, Priyadarshini Panda, 2017, 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Process variation tolerant SRAM array for ultra low voltage applications

Kaushik Roy, Jaydeep P. Kulkarni, Sang Phill Park, 2008, 2008 45th ACM/IEEE Design Automation Conference.

An Energy-Efficient High-Performance Deep-Submicron Instruction Cache

Kaushik Roy, Babak Falsafi, T. N. Vijaykumar, 2001 .

Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits

Kaushik Roy, Swarup Bhunia, Saibal Mukhopadhyay, 2005, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Test consideration for nanometer scale CMOS circuits

Kaushik Roy, Kwang-Ting Cheng, T. M. Mak, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection

Kaushik Roy, Georgios Karakonstantis, Pedro P. Irazoqui, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Decoupling capacitance allocation for power supply noise suppression

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2001, ISPD '01.

Data-dependant sense-amplifier flip-flop for low power applications

Kaushik Roy, Ashish Goel, Farshad Moradi, 2010, IEEE Custom Integrated Circuits Conference 2010.

Reading spin-torque memory with spin-torque sensors

Kaushik Roy, Anand Raghunathan, Mrigank Sharad, 2013, 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001 .

On-chip interconnect modeling by wire duplication

Kaushik Roy, Cheng-Kok Koh, Guoan Zhong, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

ge Reduction in Stacked m Double-Gate MOSFET

Kaushik Roy, Woo-Suhl Cho, 2015 .

BASED ON SHARING MULTIPLICATION

Kaushik Roy, Jongsun Park, Soonkeon Kwon, 2002 .

A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks

Chip-Hong Chang, Kaushik Roy, Xuanyao Fong, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Skewed CMOS: Noise-immune high-performance low-power static circuit family

Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar, 2000, Proceedings of the 26th European Solid-State Circuits Conference.

Self-healing design in deep scaled CMOS technologies

Kaushik Roy, Swarup Bhunia, Srikar Bhagavatula, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

Spin-Transfer Torque Memories: Devices, Circuits, and Systems

Kaushik Roy, Anand Raghunathan, Xuanyao Fong, 2016, Proceedings of the IEEE.

Estimation of inductive and resistive switching noise on power supply network in deep sub-micron CMOS circuits

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2000, Proceedings 2000 International Conference on Computer Design.

Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005 .

Dynamic supply current testing of analog circuits using wavelet transform

Kaushik Roy, Swarup Bhunia, K. Roy, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Effectiveness of low power dual-V/sub t/ designs in nano-scale technologies under process parameter variations

Kaushik Roy, Amit Agarwal, Swarup Bhunia, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Laser Induced Magnetization Reversal for Detection in Optical Interconnects

Kaushik Roy, Xuanyao Fong, Zubair Al Azim, 2014, IEEE Electron Device Letters.

Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array

Kaushik Roy, Cheng-Yi Chen, Soonkeon Kwon, 2004, Communications in Computing.

Statistical estimation of sequential circuit activity

Kaushik Roy, Tan-Li Chou, 1995, ICCAD.

Carbon Nanotube Electronics: Design of High-Performance and Low-Power Digital Circuits

Kaushik Roy, Arijit Raychowdhury, K. Roy, 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low-Power Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT

Kaushik Roy, Mrigank Sharad, Pedro P. Irazoqui, 2012, JETC.

Neuromorphic Computing Across the Stack: Devices, Circuits and Architectures

Kaushik Roy, Abhronil Sengupta, Aayush Ankit, 2018, 2018 IEEE International Workshop on Signal Processing Systems (SiPS).

An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS

Kaushik Roy, Amit Agarwal, Steven Hsu, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Approximate computing and the quest for computing efficiency

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Circuit activity based logic synthesis for low power reliable operations

Kaushik Roy, S. C. Prasad, K. Roy, 1993, IEEE Trans. Very Large Scale Integr. Syst..

Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations

Kaushik Roy, Amit Agarwal, Kunhyuk Kang, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Stress Testing: A Low Cost Alternative for Burn-in

Kaushik Roy, Abhijit Chatterjee, R. K. Roy, 1997 .

Power-Aware Testing and Test Strategies for Low Power Devices

Kaushik Roy, Xiaoqing Wen, Patrick Girard, 2008, 2008 Design, Automation and Test in Europe.

High Performance and Low Power Electronics on Flexible Substrate

Kaushik Roy, Jing Li, Aditya Bansal, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Modeling and estimation of leakage in sub-90 nm devices

Kaushik Roy, Saibal Mukhopadhyay, Arijit Raychowdhury, 2004, 17th International Conference on VLSI Design. Proceedings..

Circuit optimization for minimisation of power consumption under delay constraint

Kaushik Roy, S. C. Prasad, K. Roy, 1995, Proceedings of the 8th International Conference on VLSI Design.

Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design

Kaushik Roy, Rongtian Zhang, David B. Janes, 2001, ISLPED '01.

Write-optimized reliable design of STT MRAM

Kaushik Roy, Georgios Panagopoulos, Sumeet Kumar Gupta, 2012, ISLPED '12.

Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses pdf

Kaushik Roy, Abhronil Sengupta, K. Roy, 2015, ArXiv.

Stochastic Spin-Orbit Torque Devices as Elements for Bayesian Inference

Kaushik Roy, Shuhan Chen, Abhronil Sengupta, 2017, Scientific Reports.

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Cognitive computing with spin-based neural networks

Kaushik Roy, Mrigank Sharad, Charles Augustine, 2012, DAC Design Automation Conference 2012.

Deterministic clock gating for microprocessor power reduction

Yiran Chen, Kaushik Roy, Swarup Bhunia, 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits

Kaushik Roy, Swarup Bhunia, Saibal Mukhopadhyay, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling

Kaushik Roy, Chris H. Kim, Saibal Mukhopadhyay, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

A feasibility study of subthreshold SRAM across technology generations

Kaushik Roy, Saibal Mukhopadhyay, Arijit Raychowdhury, 2005, 2005 International Conference on Computer Design.

Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering

Kaushik Roy, Chaitali Chakrabarti, Georgios Karakonstantis, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Explainable Learning: Implicit Generative Modelling during Training for Adversarial Robustness pdf

Kaushik Roy, Priyadarshini Panda, 2018, ArXiv.

An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs

Kaushik Roy, Jing Li, Swaroop Ghosh, 2008, JETC.

Layout-aware optimization of stt mrams

Kaushik Roy, Sumeet Kumar Gupta, Sang Phill Park, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Issues in logic synthesis for delay and bridging faults

Kaushik Roy, Abhijit Chatterjee, Jacob A. Abraham, 1990, IEEE International Symposium on Circuits and Systems.

Selective notifications based on message priority determination

Kaushik Roy, Yi Zhou, Timothy Sohn, 2018 .

Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits

Kaushik Roy, Aditya Bansal, Jayathi Murthy, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A graph theoretic approach for design and synthesis of multiplierless FIR filters

Kaushik Roy, Khurram Muhammad, 1999, Proceedings 12th International Symposium on System Synthesis.

Design and optimization of low voltage high performance dual threshold CMOS circuits

Mark C. Johnson, Kaushik Roy, Mark Johnson, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks

Kaushik Roy, Parami Wijesinghe, Gopalakrishnan Srinivasan, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Circuit activity driven multilevel logic optimization for low power reliable operation

Kaushik Roy, Sharat Prasad, 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

Stage number optimization for switched capacitor power converters in micro-scale energy harvesting

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2011, 2011 Design, Automation & Test in Europe.

Data-retention flip-flops for power-down applications

Kaushik Roy, Hamid Mahmoodi, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

A Low-Complexity Scan Reordering Algorithm for Low Power Test-Per-Scan BIST

Kaushik Roy, Swarup Bhunia, Debjyoti Ghosh, 2004 .

An Optimal Algorithm for Low Power Multiplierless FIR Filter Design using Chebychev Criterion

Kaushik Roy, Georgios Karakonstantis, 2007, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07.

MRPF: an architectural transformation for synthesis of high-performance and low-power digital filters

Kaushik Roy, Hunsoo Choo, Khurram Muhammad, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Robust high-performance low-power carry select adder

Kaushik Roy, Woopyo Jeong, 2003, ASP-DAC '03.

Fault Detection and Location Using IDD Waveform Analysis

Kaushik Roy, Khurram Muhammad, K. Muhammad, 2001, IEEE Des. Test Comput..

Power sensitivity-a new method to estimate power dissipation considering uncertain specifications of primary inputs

Kaushik Roy, Tan-Li Chou, Zhanping Chen, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs

Kaushik Roy, Sumeet Kumar Gupta, 2013, IEEE Design & Test.

Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies

Kaushik Roy, Swaroop Ghosh, Saibal Mukhopadhyay, 2006, 2006 IEEE International SOC Conference.

On Channel Architecture and Routability for FPGAs Under Faulty Conditions

Kaushik Roy, Sudip Nag, 1994, FPL.

Efficient Hybrid Network Architectures for Extremely Quantized Neural Networks Enabling Intelligence at the Edge pdf

Kaushik Roy, Indranil Chakraborty, Deboleena Roy, 2019, ArXiv.

A novel multiple-valued logic design using ballistic carbon nanotube FETs

Kaushik Roy, Arijit Raychowdhury, 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

LVDCSL: low voltage differential current switch logic, a robust low power DCSL family

Kaushik Roy, Dinesh Somasekhar, 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis

Kaushik Roy, Elena I. Vatajelu, Georgios Panagopoulos, 2010, 2010 15th IEEE European Test Symposium.

Power Constrained Test Scheduling with Low Power Weighted Random Testing

Kaushik Roy, Xiaodong Zhang, 2001, IOLTW.

Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC

Kaushik Roy, Anand Raghunathan, Xuanyao Fong, 2015, ACM J. Emerg. Technol. Comput. Syst..

Multiple scan chain design technique for power reduction during test application in BIST

Kaushik Roy, Swarup Bhunia, Debjyoti Ghosh, 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

Tree-CNN: A Deep Convolutional Neural Network for Lifelong Learning pdf

Kaushik Roy, Priyadarshini Panda, Deboleena Roy, 2018, ArXiv.

Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices

Kaushik Roy, Karthik Yogendra, Mrigank Sharad, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2006, TODE.

Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives

Kaushik Roy, Karthik Yogendra, Anand Raghunathan, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Low power adder with adaptive supply voltage

Kaushik Roy, Hiroaki Suzuki, Woopyo Jeong, 2003, Proceedings 21st International Conference on Computer Design.

Power supply noise-aware scheduling and allocation for DSP synthesis

Yiran Chen, Kaushik Roy, Dongku Kang, 2005, Sixth international symposium on quality electronic design (isqed'05).

Complexity reduction of digital filters using shift inclusive differential coefficients

Kaushik Roy, Hunsoo Choo, Khurram Muhammad, 2004, IEEE Transactions on Signal Processing.

Iterative Wirability and Performance Improvement for FPGAs

Kaushik Roy, Sudip Nag, 1993, 30th ACM/IEEE Design Automation Conference.

Power reduction in test-per-scan BIST with supply gating and efficient scan partitioning

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, Sixth international symposium on quality electronic design (isqed'05).

LALM: a logic-aware layout methodology to enhance the noise immunity of domino circuits

Kaushik Roy, Yonghee Im, K. Roy, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Stochastic Spiking Neural Networks Enabled by Magnetic Tunnel Junctions: From Nontelegraphic to Telegraphic Switching Regimes

Kaushik Roy, Chamika M. Liyanagedera, Abhronil Sengupta, 2017 .

Exploring Spin Transfer Torque Devices for Unconventional Computing

Kaushik Roy, Mrigank Sharad, Xuanyao Fong, 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Frequency domain analysis of switching noise on power supply network

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Accurate characterization of random process variations using a robust low-voltage high-sensitivity sensor featuring replica-bias circuit

Kaushik Roy, Ashish Goel, Jaydeep P. Kulkarni, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

A NewParadigm forLow-power, Variation-Tolera nt Circuit Synthesis UsingCritical PathIsolation

Kaushik Roy, Swaroop Ghosh, Swarup Bhunia, 2006 .

Estimation of power dissipation using a novel power macromodelingtechnique

Kaushik Roy, Edwin K. P. Chong, Zhanping Chen, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes

Kaushik Roy, Anand Raghunathan, Rangharajan Venkatesan, 2016, ACM J. Emerg. Technol. Comput. Syst..

Memories in Scaled technologies: A Review of Process Induced Failures, Test methodologies, and Fault Tolerance

Kaushik Roy, Saibal Mukhopadhyay, Qikai Chen, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

A Low Effort Approach to Structured CNN Design Using PCA

Kaushik Roy, Priyadarshini Panda, Isha Garg, 2018, IEEE Access.

Low Power VLSI Signal Processing

Kaushik Roy, Khurram Muhammad, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Exploring Boolean and Non-Boolean Computing Applications of Spin Torque Devices pdf

Kaushik Roy, Karthik Yogendra, Mrigank Sharad, 2013, ArXiv.

Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling

Kaushik Roy, Anand Raghunathan, Srimat T. Chakradhar, 2013, TECS.

Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies

Kaushik Roy, Arijit Raychowdhury, K. Roy, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

QSERL: quasi-static energy recovery logic

Kaushik Roy, Yibin Ye, 2001 .

Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style

Kaushik Roy, Hamid Mahmoodi, K. Roy, 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

Minimizing ohmic loss in future processor IR events

Kaushik Roy, Mark M. Budnik, M. Budnik, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques

Kaushik Roy, Liqiong Wei, Zhanping Chen, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI

Kaushik Roy, Kunhyuk Kang, Haldun Kufluoglu, 2006, 2006 International Conference on Computer Design.

Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2001, ISLPED '01.

The Applicability of IDD Waveform Analysis to Testing of CMOS Circuits

Kaushik Roy, Hendrawan Soeleman, Dinesh Somasekhar, 1997 .

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates

Kaushik Roy, Seong-Ook Jung, Myeong-Eun Hwang, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing

Kaushik Roy, Mrigank Sharad, Deliang Fan, 2014, IEEE Transactions on Neural Networks and Learning Systems.

Low power reconfigurable DCT design based on sharing multiplication

Kaushik Roy, Jongsun Park, Soonkeon Kwon, 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Coping with Variations through System-Level Design

Kaushik Roy, Sujit Dey, Swaroop Ghosh, 2009, 2009 22nd International Conference on VLSI Design.

Functional analysis of circuits under timing variations

Kaushik Roy, Anand Raghunathan, Görschwin Fey, 2012, 2012 17th IEEE European Test Symposium (ETS).

Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching

Kaushik Roy, Tan-Li Chou, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Efficient statistical approach to estimate power considering uncertain properties of primary inputs

Kaushik Roy, Tan-Li Chou, Zhanping Chen, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Memory-based embedded digital ATE

Kaushik Roy, Ashish Goel, Dongsoo Lee, 2011, 29th VLSI Test Symposium.

Dual-edge triggered level converting flip-flops

Kaushik Roy, Hamid Mahmoodi, K. Roy, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Energy recovery clocking scheme and flip-flops for ultra low-energy applications

Kaushik Roy, Hamid Mahmoodi, Matthew Cooke, 2003, ISLPED '03.

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture

Kaushik Roy, Yusung Kim, Kon-Woo Kwon, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Maximum power estimation for CMOS circuits using deterministic and statistical approaches

Kaushik Roy, Chuan-Yu Wang, 1998, IEEE Trans. Very Large Scale Integr. Syst..

An adaptive window-based susceptance extraction and its efficient implementation

Kaushik Roy, Cheng-Kok Koh, Venkataramanan Balakrishnan, 2003, DAC '03.

Self-Repairing SRAM Using On-Chip Detection and Compensation

Kaushik Roy, Ching-Te Chuang, Saibal Mukhopadhyay, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Ultra-low-power DLMS adaptive filter for hearing aid applications

Kaushik Roy, Hendrawan Soeleman, Chris Hyung-Il Kim, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Test challenges for deep sub-micron technologies

Kaushik Roy, Sujit Dey, Kwang-Ting Cheng, 2000, Proceedings - Design Automation Conference.

Statistical modeling of pipeline delay and design of pipeline under process variation to enhance yield in sub-100nm technologies

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2005, Design, Automation and Test in Europe.

Automatic synthesis of FPGA channel architecture for routability and performance

Kaushik Roy, Sudip Nag, 1994, IEEE Trans. Very Large Scale Integr. Syst..

Discretization Based Solutions for Secure Machine Learning Against Adversarial Attacks

Kaushik Roy, Indranil Chakraborty, Priyadarshini Panda, 2019, IEEE Access.

Floorplan-aware low-complexity digital filter synthesis for low-power & high-speed

Kaushik Roy, Hunsoo Choo, Dongku Kang, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling

Kaushik Roy, Myeong-Eun Hwang, Tamer Cakici, 2007, DATE.

Statistical timing analysis using levelized covariance propagation

Kaushik Roy, Bipul Chandra Paul, Kunhyuk Kang, 2005, Design, Automation and Test in Europe.

Skewed CMOS: noise-tolerant high-performance low-power static circuit family

Kaushik Roy, Dinesh Somasekhar, Naran Sirisantana, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Guest Editorial

Kaushik Roy, Alex Orailoglu, Clifford Lau, 2007, IEEE Trans. Circuits Syst. I Regul. Pap..

Improved clock-gating control scheme for transparent pipeline

Kaushik Roy, Aurobindo Dasgupta, Byung Guk Kim, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Estimating Circuit Activity in Combinational CMOS Digital Circuits

Kaushik Roy, Tan-Li Chou, Hendrawan Soeleman, 2000, IEEE Des. Test Comput..

Computing-in-memory with spintronics

Kaushik Roy, Anand Raghunathan, Sachin S. Sapatnekar, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Viterbi-Based Efficient Test Data Compression

Kaushik Roy, Dongsoo Lee, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Architecture and performance of 3-dimensional SOI circuits

Kaushik Roy, Rongtian Zhang, D. B. Janes, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling

Kaushik Roy, Khurram Muhammad, K. Roy, 2002, IEEE Trans. Very Large Scale Integr. Syst..

SALSA: Systematic logic synthesis of approximate circuits

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2012, DAC Design Automation Conference 2012.

Low power and compact mixed-mode signal processing hardware using spin-neurons

Kaushik Roy, Mrigank Sharad, Deliang Fan, 2013, International Symposium on Quality Electronic Design (ISQED).

Efficient Design of Micro-Scale Energy Harvesting Systems

Kaushik Roy, Chao Lu, Vijay Raghunathan, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Variation-aware and self-healing design methodology for a system-on-chip

Kaushik Roy, Srikar Bhagavatula, Byunghoo Jung, 2012, 2012 13th Latin American Test Workshop (LATW).

StoRM: A Stochastic Recognition and Mining processor

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

On Routability for FPGAs under Faulty Conditions

Kaushik Roy, Sudip Nag, 1995, IEEE Trans. Computers.

An energy recovery static RAM memory core

Kaushik Roy, Yibin Ye, Dinesh Somasekhar, 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

"All Programmable SOC FPGA for networking and computing in big data infrastructure"

Kaushik Roy, Georges G. E. Gielen, Ivo Bolsens, 2014, ASP-DAC.

Energy-Efficient and Improved Image Recognition with Conditional Deep Learning

Kaushik Roy, Priyadarshini Panda, Abhronil Sengupta, 2017, ACM J. Emerg. Technol. Comput. Syst..

Energy-Efficient Neural Computing with Approximate Multipliers

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2018, ACM J. Emerg. Technol. Comput. Syst..

Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals

Kaushik Roy, Himanshu Markandeya, K. Roy, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, Sixth international symposium on quality electronic design (isqed'05).

Toward a spintronic deep learning spiking neural processor

Kaushik Roy, Bing Han, Abhronil Sengupta, 2016, 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Modeling of failure probability and statistical design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) array for yield enhancement

Kaushik Roy, Jing Li, Charles Augustine, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput

Kaushik Roy, Amit Agarwal, Patrick Ndai, 2008, IEEE Transactions on Computers.

Algorithms for low power FIR filter realization using differential coefficients

Kaushik Roy, Debashis Bhattacharya, Naushik Sankarayya, 1997, Proceedings Tenth International Conference on VLSI Design.

Ultralow Power Computing with Sub-threshold Leakage: A Comparative Study of Bulk and SOI Technologies

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Stochastic wire-length and delay distributions of 3-dimensional circuits

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Simulation studies of an All-Spin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets pdf

Kaushik Roy, Abhronil Sengupta, Yong Shim, 2015, ArXiv.

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

Kaushik Roy, Jae-Joon Kim, Ik Joon Chang, 2009, IEEE Journal of Solid-State Circuits.

A soft error monitor using switching current detection

Kaushik Roy, Amit Agarwal, Patrick Ndai, 2005, 2005 International Conference on Computer Design.

Convolving over time via recurrent connections for sequential weight sharing in neural networks

Kaushik Roy, Jason M. Allred, K. Roy, 2017, 2017 International Joint Conference on Neural Networks (IJCNN).

Approximate storage for energy efficient spintronic memories

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Ultra low voltage CMOS

Kaushik Roy, 2009, ISLPED.

Integrated test solutions and test economics for MCMs

Kaushik Roy, Kevin T. Kornegay, 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

Kaushik Roy, Hamid Mahmoodi, Matthew Cooke, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A technique to reduce power and test application time in BIST

Kaushik Roy, Swarup Bhunia, Debjyoti Ghosh, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Design of power-efficient approximate multipliers for approximate artificial neural networks

Kaushik Roy, Lukás Sekanina, Zdenek Vasícek, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Neuromorphic Computing Enabled by Spin-Transfer Torque Devices

Kaushik Roy, Anand Raghunathan, Priyadarshini Panda, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

Reliability Implications of Bias-Temperature Instability in Digital ICs

Kaushik Roy, Sang Phill Park, Kunhyuk Kang, 2009, IEEE Design & Test of Computers.

Synthesis of selectively clocked skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2002, Proceedings International Symposium on Quality Electronic Design.

On fault modeling and fault tolerance of antifuse based FPGAs

Kaushik Roy, 1993, 1993 IEEE International Symposium on Circuits and Systems.

Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking

Kaushik Roy, Swaroop Ghosh, Georgios Karakonstantis, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Ultra low energy analog image processing using spin based neurons

Kaushik Roy, Mrigank Sharad, Charles Augustine, 2012, 2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy

Kaushik Roy, Jongsun Park, Jung Hwan Choi, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Asymmetric halo CMOSFET to reduce static power dissipation with improved performance

Kaushik Roy, Aditya Bansal, K. Roy, 2005, IEEE Transactions on Electron Devices.

Design of sigma-delta modulators with arbitrary transfer functions

Kaushik Roy, Khurram Muhammad, Yongtao Wang, 2005, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005..

Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis

Kaushik Roy, Christos A. Papachristou, Francis G. Wolff, 2013, IEEE Transactions on Computers.

Low power design under parameter variations

Kaushik Roy, Swarup Bhunia, K. Roy, 2008, 2008 IEEE International SOC Conference.

A Novel Approach to Accurate Timing Verification Using RTL Descriptions

Kaushik Roy, Jacob A. Abraham, 1989, 26th ACM/IEEE Design Automation Conference.

Power trends and performance characterization of 3-dimensional integration

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Estimating Area Efficiency of Antifuse based Channeled FPGA Architectures

Kaushik Roy, Mahesh Mehendale, 1993, The Sixth International Conference on VLSI Design.

Estimation of power sensitivity in sequential circuits with power macromodeling application

Kaushik Roy, Edwin K. P. Chong, Zhanping Chen, 1998, ICCAD.

The effect of process variation on device temperature in finFET circuits

Kaushik Roy, Jayathi Murthy, Jung Hwan Choi, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

A Priority-Based 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications

Kaushik Roy, Debabrata Mohapatra, Ik Joon Chang, 2011, IEEE Transactions on Circuits and Systems for Video Technology.

Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator

Chip-Hong Chang, Kaushik Roy, Xuanyao Fong, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

AxNN: Energy-efficient neuromorphic systems using approximate computing

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

A logic-aware layout methodology to enhance the noise immunity of domino circuits

Kaushik Roy, Yonghee Im, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations

Kaushik Roy, Jaydeep P. Kulkarni, Mesut Meterelliyoz, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Cache Design with Domain Wall Memory

Kaushik Roy, Anand Raghunathan, Mrigank Sharad, 2016, IEEE Transactions on Computers.

Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing pdf

Kaushik Roy, Abhronil Sengupta, K. Roy, 2017, ArXiv.

Channel architecture optimization for performance and routability of row-based FPGAs

Kaushik Roy, Santanu Dutta, Sudip Nag, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Design and synthesis of low power weighted random pattern generator considering peak power reduction

Kaushik Roy, Xiaodong Zhang, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors

Kaushik Roy, Chris H. Kim, 2002, ISLPED '02.

Cascaded carry-select adder (C/sup 2/SA): a new structure for low-power CSA design

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Mixed-Vth (MVT) CMOS circuit design methodology for low power applications

Kaushik Roy, Vivek De, Liqiong Wei, 1999, DAC '99.

Profit Aware Circuit Design Under Process Variations Considering Speed Binning

Kaushik Roy, Animesh Datta, Swarup Bhunia, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low complexity FIR filters using factorization of perturbed coefficients

Kaushik Roy, Khurram Muhammad, Cassondra Neau, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Low-power scan design using first-level supply gating

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Spintronic Switches for Ultralow Energy On-Chip and Interchip Current-Mode Interconnects

Kaushik Roy, Mrigank Sharad, K. Roy, 2013, IEEE Electron Device Letters.

An 8×8 sub-threshold digital CMOS carry save array multiplier

Kaushik Roy, Bipul C. Paul, Hendrawan Soeleman, 2001 .

Estimation of switching noise on power supply lines in deep sub-micron CMOS circuits

Kaushik Roy, Shiyou Zhao, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

POWERTEST: a tool for energy conscious weighted random pattern testing

Kaushik Roy, Sudipta Bhawmik, Xiaodong Zhang, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

A forward body-biased low-leakage SRAM cache: device and architecture considerations

Kaushik Roy, Chris H. Kim, Saibal Mukhopadhyay, 2003, ISLPED '03.

Gabor filter assisted energy efficient fast learning Convolutional Neural Networks

Kaushik Roy, Priyadarshini Panda, Syed Shakib Sarwar, 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

Kaushik Roy, Sang Phill Park, Kunhyuk Kang, 2008, 2008 Asia and South Pacific Design Automation Conference.

Going Deeper in Spiking Neural Networks: VGG and Residual Architectures

Kaushik Roy, Abhronil Sengupta, Robert Wang, 2018, Front. Neurosci..

A power macromodeling technique based on power sensitivity

Kaushik Roy, Zhanping Chen, K. Roy, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Design of low voltage CMOS circuits

Kaushik Roy, R. Krishnammthy, 2001, Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573).

Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2003, ISLPED '03.

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001

Kaushik Roy, Cheng-Kok Koh, Sung-Mo Steve Kang, 2001, ACM Great Lakes Symposium on VLSI.

Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective

Kaushik Roy, Arijit Raychowdhury, Sumeet Kumar Gupta, 2010, Proceedings of the IEEE.

Dynamic Bit-width Adaptation in DCT: Image Quality versus Computation Energy Trade-off

Kaushik Roy, Jongsun Park, Jung Hwan Choi, 2006, Proceedings of the Design Automation & Test in Europe Conference.

DCT processor architecture based on computation sharing

Kaushik Roy, Jongsun Park, Soonkeon Kwon, 2002, ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605).

Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement

Kaushik Roy, Kunhyuk Kang, Muhammad Ashraful Alam, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Containing the Nanometer “Pandora-Box”: Cross-Layer Design Techniques for Variation Aware Low Power Systems

Kaushik Roy, Abhijit Chatterjee, Georgios Karakonstantis, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

DWM-TAPESTRI - An energy efficient all-spin cache using domain wall shift based writes

Kaushik Roy, Anand Raghunathan, Mrigank Sharad, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

FinFET SRAM - device and circuit design considerations

Kaushik Roy, Aditya Bansal, Hari Ananthan, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Leakage control with efficient use of transistor stacks in single threshold CMOS

Mark C. Johnson, Kaushik Roy, Lih-Yih Chiou, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Significance driven computation on next-generation unreliable platforms

Kaushik Roy, Vaibhav Gupta, Georgios Karakonstantis, 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design

Kaushik Roy, Amit Agarwal, Saibal Mukhopadhyay, 2006, IEEE Custom Integrated Circuits Conference 2006.

Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications

Kaushik Roy, Anand Raghunathan, A. Raghunathan, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Minimizing Ohmic Loss and Supply Voltage Variation Using a Novel Distributed Power Supply Network

Kaushik Roy, Mark M. Budnik, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Statistical design and optimization of SRAM cell for yield enhancement

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Design in the nano-scale Era: Low-power, reliability, and error resiliency

Kaushik Roy, 2009, 2009 IEEE International SOC Conference (SOCC).

Robust Level Converter for Sub-Threshold/Super-Threshold Operation:100 mV to 2.5 V

Kaushik Roy, Jae-Joon Kim, Ik Joon Chang, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices

Kaushik Roy, Ashish Goel, Animesh Datta, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Brain-inspired computing with spin torque devices

Kaushik Roy, Karthik Yogendra, Mrigank Sharad, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Low-Power SRAM Using Bit-Line Charge-Recycling

Kaushik Roy, Hamid Mahmoodi, Keejong Kim, 2008, IEEE Journal of Solid-State Circuits.

Computing approximately, and efficiently

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code

Kaushik Roy, Dongsoo Lee, Sang Phill Park, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

The effect of multiple charge-discharge paths on testing of BiCMOS logic circuits

Kaushik Roy, J. A. Abraham, M. E. Levitt, 1992, [1992] Proceedings The European Conference on Design Automation.

Computing with coupled Spin Torque Nano Oscillators

Kaushik Roy, Karthik Yogendra, Minsuk Koo, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor

Kaushik Roy, Franco Stellari, Peilin Song, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design for burn-in test: A technique for burn-in thermal stability under die-to-die parameter variations

Kaushik Roy, Mesut Meterelliyoz, 2009, 2009 Asia and South Pacific Design Automation Conference.

Fine-Grained Redundancy in Adders

Kaushik Roy, Patrick Ndai, Shih-Lien Lu, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

A CMOS thermal sensor and its applications in temperature adaptive design

Kaushik Roy, Mesut Meterelliyoz, Qikai Chen, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Spin-Transfer Torque Magnetic neuron for low power neuromorphic computing

Kaushik Roy, Abhronil Sengupta, K. Roy, 2015, 2015 International Joint Conference on Neural Networks (IJCNN).

Low-Power CMOS VLSI Circuit Design

Kaushik Roy, Sharat Prasad, K. Roy, 2000 .

Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal

Kaushik Roy, Karthik Yogendra, Minsuk Koo, 2017, 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning

Kaushik Roy, Georgios Karakonstantis, Debabrata Mohapatra, 2009, 2009 IEEE Workshop on Signal Processing Systems.

Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS

Kaushik Roy, Chris H. Kim, Hari Ananthan, 2004, ISLPED '04.

VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture

Kaushik Roy, Vaibhav Gupta, Georgios Karakonstantis, 2010, 2010 IEEE International Conference on Computer Design.

A High Performance, Scalable Multiplexed Keeper Technique

Kaushik Roy, Jaydeep P. Kulkarni, K. Roy, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

A Low Power High Performance Multiplexed Keeper Technique

Kaushik Roy, Jaydeep P. Kulkarni, 2006 .

Device/circuit/architecture co-design of reliable STT-MRAM

Kaushik Roy, Xuanyao Fong, Zoha Pajouhi, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Design of Sigma–Delta Modulators With Arbitrary Transfer Functions

Kaushik Roy, Khurram Muhammad, Yongtao Wang, 2007, IEEE Transactions on Signal Processing.

Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing

Kaushik Roy, Georgios Karakonstantis, Nilanjan Banerjee, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Tolerance to Small Delay Defects by Adaptive Clock Stretching

Kaushik Roy, Swaroop Ghosh, Patrick Ndai, 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).

A novel fault tolerant cache to improve yield in nanometer technologies

Kaushik Roy, Amit Agarwal, Bipul Chandra Paul, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Spin torque nano-oscillator based Oscillatory Neural Network

Kaushik Roy, Karthik Yogendra, Chamika M. Liyanagedera, 2016, 2016 International Joint Conference on Neural Networks (IJCNN).

A 160 mV Robust Schmitt Trigger Based

Kaushik Roy, Jaydeep P. Kulkarni, Keejong Kim, 2007 .

REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN

Kaushik Roy, Patrick Ndai, Ashish Goel, 2009, 2009 IEEE Custom Integrated Circuits Conference.

Approximate computing: An integrated hardware approach

Kaushik Roy, Anand Raghunathan, Swagath Venkataramani, 2013, 2013 Asilomar Conference on Signals, Systems and Computers.

Digital CMOS logic operation in the sub-threshold region

Kaushik Roy, Hendrawan Soeleman, 2000, ACM Great Lakes Symposium on VLSI.

Low complexity digital signal processing system design techniques

Kaushik Roy, Jongsun Park, 2005 .

Decision feedback equalizer with two's complement computation sharing multiplication

Kaushik Roy, Hunsoo Choo, Khurram Muhammad, 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

Approximate computing for energy-efficient error-resilient multimedia systems

Kaushik Roy, 2013, DDECS.

High-performance FIR filter design based on sharing multiplication

Kaushik Roy, Khurram Muhammad, Jongsun Park, 2003, IEEE Trans. Very Large Scale Integr. Syst..

Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing

Kaushik Roy, Nilanjan Banerjee, 2007, J. Low Power Electron..

Automatic Test Reordering for Electrical and Thermal Stress during Monitored Burn-in

Kaushik Roy, Abhijit Chatterjee, Rabindra K. Roy, 1994 .

Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection

Kaushik Roy, Pedro P. Irazoqui, Himanshu Markandeya, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A circuit-compatible model of ballistic carbon nanotube field-effect transistors

Kaushik Roy, Saibal Mukhopadhyay, Arijit Raychowdhury, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Energy-efficient recognition and mining processor using scalable effort design

Kaushik Roy, Anand Raghunathan, Debabrata Mohapatra, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Sensitivity of power dissipation to uncertainties in primary input specification

Kaushik Roy, Z.-P. Chen, T.-L. Chou, 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation

Kaushik Roy, Swarup Bhunia, Arijit Raychowdhury, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fusion-FlowNet: Energy-Efficient Optical Flow Estimation using Sensor Fusion and Deep Fused Spiking-Analog Network Architectures pdf

Kaushik Roy, Chankyu Lee, Adarsh Kumar Kosta, 2021, 2022 International Conference on Robotics and Automation (ICRA).

Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper

Kaushik Roy, Wenqin Huangfu, Hussam Amrouch, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

One Timestep is All You Need: Training Spiking Neural Networks with Ultra Low Latency pdf

Kaushik Roy, Sayeed Shafayet Chowdhury, Nitin Rathi, 2021, ArXiv.

Gradient Projection Memory for Continual Learning pdf

Kaushik Roy, Gobinda Saha, Isha Garg, 2021, ICLR.

Accurate and Accelerated Neuromorphic Network Design Leveraging A Bayesian Hyperparameter Pareto Optimization Approach

Catherine D. Schuman, Steven R. Young, Kaushik Roy, 2021, ICONS.

Network Compression via Mixed Precision Quantization Using a Multi-Layer Perceptron for the Bit-Width Allocation

Kaushik Roy, Efstathia Soufleri, 2021, IEEE Access.

Multi-Level Neuromorphic Devices Built on Emerging Ferroic Materials: A Review

Kaushik Roy, Amogh Agrawal, Eunseon Yu, 2021, Frontiers in Neuroscience.

Energy efficient 'in memory' computing to enable decentralised service workflow composition in support of multi-domain operations

Kaushik Roy, Ian Taylor, Abbas Rahimi, 2021, Defense + Commercial Sensing.

On the Intrinsic Robustness of NVM Crossbars Against Adversarial Attacks

Kaushik Roy, Deboleena Roy, Timur Ibrayev, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

NAX: Co-Designing Neural Network and Hardware Architecture for Memristive Xbar based Computing Systems pdf

Kaushik Roy, Shubham Negi, Aayush Ankit, 2021, ArXiv.

IMPULSE: A 65-nm Digital Compute-in-Memory Macro With Fused Weights and Membrane Potential for Spike-Based Sequential Learning Tasks

Kaushik Roy, Minsuk Koo, Akhilesh Jaiswal, 2021, IEEE Solid-State Circuits Letters.

Spatio-Temporal Pruning and Quantization for Low-latency Spiking Neural Networks

Kaushik Roy, Sayeed Shafayet Chowdhury, Isha Garg, 2021, 2021 International Joint Conference on Neural Networks (IJCNN).

Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and Perspectives

Kaushik Roy, Amogh Agrawal, Nitin Rathi, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Magnetoresistive Circuits and Systems: Embedded Non-Volatile Memory to Crossbar Arrays

Kaushik Roy, Amogh Agrawal, Tanvi Sharma, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Implicit adversarial data augmentation and robustness with Noise-based Learning

Kaushik Roy, Priyadarshini Panda, 2021, Neural Networks.

Embracing Stochasticity to Enable Neuromorphic Computing at the Edge

Kaushik Roy, Deboleena Roy, Amogh Agrawal, 2021, IEEE Design & Test.

Oscillatory Fourier Neural Network: A Compact and Efficient Architecture for Sequential Processing pdf

Kaushik Roy, Bing Han, Cheng Wang, 2021, AAAI.

Editorial: Understanding and Bridging the Gap Between Neuromorphic Computing and Machine Learning

Kaushik Roy, Lei Deng, Huajin Tang, 2021, Frontiers in Computational Neuroscience.

Enabling Robust SOT-MTJ Crossbars for Machine Learning using Sparsity-Aware Device-Circuit Co-design

Kaushik Roy, Amogh Agrawal, Tanvi Sharma, 2021, 2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

Spiking Neural Networks with Improved Inherent Recurrence Dynamics for Sequential Learning pdf

Kaushik Roy, Wachirawit Ponghiran, K. Roy, 2021, AAAI.

Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators

Dejan S. Milojicic, Kaushik Roy, Paolo Faraboschi, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

Power Sensitivity-A New Method to Estimate Power ConsideringUncertain Speci cations of Primary Inputs

Kaushik Roy, Zhanping Chen, 1997 .

Write-Optimized STT-MRAM Bit-Cells Using Asymmetrically Doped Transistors

Kaushik Roy, Sri Harsha Choday, S. H. Choday, 2014, IEEE Electron Device Letters.

Prospects of Thin-Film Thermoelectric Devices for Hot-Spot Cooling and On-Chip Energy Harvesting

Kaushik Roy, Mark S. Lundstrom, Sri Harsha Choday, 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

A non-volatile cascadable magneto-electric material implication logic

Kaushik Roy, Akhilesh Jaiswal, Indranil Chakraborty, 2017, 2017 75th Annual Device Research Conference (DRC).

PETE : Purdue Emerging Technology Evaluator

Kaushik Roy, Charles Augustine, Arijit Raychowdhury, 2007 .

Spintronic switches for ultra low energy global interconnects

Kaushik Roy, Mrigank Sharad, K. Roy, 2014 .

Roadmap on emerging hardware and technology for machine learning

Kaushik Roy, Yuchao Yang, Alberto Salleo, 2020, Nanotechnology.

Ultra-High Density, High-Performance and Energy-Efficient All Spin Logic

Kaushik Roy, Karthik Yogendra, Mrigank Sharad, 2013 .

Asymmetric halo CMOSFET to reduce static power dissipation with improved performance

Kaushik Roy, Aditya Bansal, K. Roy, 2005 .

Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Current

Kaushik Roy, Swarup Bhunia, .

Non-Volatile Complementary Polarizer Spin-Transfer Torque On-Chip Caches: A Device/Circuit/Systems Perspective

Kaushik Roy, Anand Raghunathan, Xuanyao Fong, 2014, IEEE Transactions on Magnetics.

Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations

Kaushik Roy, Niladri N. Mojumder, Sumeet K. Gupta, 2011, 69th Device Research Conference.

Very Low-Complexity Digital Filters Based On Computational Redundancy Reduction

Kaushik Roy, Khurram Muhammad, K. Muhammad, 1999 .

Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance

Kaushik Roy, Saibal Mukhopadhyay, Arijit Raychowdhury, 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..

Perovskite nickelates as bio-electronic interfaces

Kaushik Roy, Gobinda Saha, Hua Zhou, 2019, Nature Communications.

Double-gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM

Kaushik Roy, Meng-Hsueh Chiang, Aditya Bansal, 2009, 2009 Device Research Conference.

Neuromorphic computing enabled by physics of electron spins: Prospects and perspectives

Kaushik Roy, Abhronil Sengupta, K. Roy, 2018 .

Area-Efficient SOT-MRAM With a Schottky Diode

Kaushik Roy, Yeongkyo Seo, Kon-Woo Kwon, 2016, IEEE Electron Device Letters.

SPICE Models for Magnetic Tunnel Junctions Based on Monodomain Approximation

Kaushik Roy, Xuanyao Fong, Charles Augustine, 2013 .

Physics-Based Compact Modeling of Successive Breakdown in Ultrathin Oxides

Kaushik Roy, Chih-Hsiang Ho, Soo Youn Kim, 2015, IEEE Transactions on Nanotechnology.

Spatial and Temporal Correlations

Kaushik Roy, Tan-Li Chou, 1995 .

Statistical SBD Modeling and Characterization and Its Impact on SRAM Cells

Kaushik Roy, Chih-Hsiang Ho, Soo Young Kim, 2014, IEEE Transactions on Electron Devices.

Generating true random numbers using on-chip complementary polarizer spin-transfer torque magnetic tunnel junctions

Kaushik Roy, Xuanyao Fong, Mei-Chin Chen, 2014, 72nd Device Research Conference.

INVITED : A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era

Kaushik Roy, Michael Niemier, Sachin S. Sapatnekar, 2017 .

Modeling and Evaluation of Topological Insulator/Ferromagnet Heterostructure-Based Memory

Kaushik Roy, Xuanyao Fong, Ahmed Kamal Reza, 2016, IEEE Transactions on Electron Devices.

Maximum power estimation for CMOS circuits under arbitrary delay model

Kaushik Roy, C.-Y. Wang, T.-L. Chou, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits

Kaushik Roy, Chuan-Yu Wang, 1997, ICCAD 1997.

SUBTHRESHOLD LEAKAGE CONTROL BY MULTIPLE CHANNEL LENGTH CMOS (McCMOS)

Mark C. Johnson, Kaushik Roy, 1997 .

Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs

Kaushik Roy, Anand Raghunathan, Rangharajan Venkatesan, 2016, IEEE Transactions on Electron Devices.

Design Space Exploration of Hysteresis-Free HfZrOx-Based Negative Capacitance FETs

Kaushik Roy, K. Roy, Ankit Sharma, 2017, IEEE Electron Device Letters.

Algorithmic and architectural techniques for low-power digital signal processing

Kaushik Roy, Khurram Muhammad, 1999 .

Stochastic Modeling of Positive Bias Temperature Instability in High- $\kappa $ Metal Gate nMOSFETs

Kaushik Roy, Chih-Hsiang Ho, Mohammad Khaled Hassan, 2014, IEEE Transactions on Electron Devices.

Analysis of Stability Degradation of SRAMs Using a Physics-Based PBTI Model

Kaushik Roy, Chih-Hsiang Ho, Soo Youn Kim, 2014, IEEE Electron Device Letters.

Purdue Nanoelectronics Research Laboratory Magnetic Tunnel Junction Model

Kaushik Roy, Xuanyao Fong, Charles Augustine, 2014 .

Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation

Kaushik Roy, Saibal Mukhopadhyay, Arijit Raychowdhury, 2003, ICCAD 2003.

True random number generation using voltage controlled spin-dice

Kaushik Roy, Abhronil Sengupta, Akhilesh Jaiswal, 2016, 2016 74th Annual Device Research Conference (DRC).

Stochastic Interconnect Modeling , Power Trends , and Performance Characterization of 3-Dimensional Circuits

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001 .

A physical model to predict STT-MRAM performance degradation induced by TDDB

Kaushik Roy, Chih-Hsiang Ho, Georgios D. Panagopoulos, 2013, 71st Device Research Conference.

Exploring the design of ultra-low energy global interconnects based on spin-torque switches

Kaushik Roy, Mrigank Sharad, Xuanyao Fong, 2013, 2013 IEEE International Electron Devices Meeting.

P-channel Tunneling Field Effect Transistor (TFET): Sub-10nm technology enablement by GaSb-InAs with doped source underlap

Kaushik Roy, A. Arun Goud, Ankit Sharma, 2015, 2015 73rd Annual Device Research Conference (DRC).

Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs

Kaushik Roy, Sri Harsha Choday, A. Arun Goud, 2013, 71st Device Research Conference.

Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems

Kaushik Roy, D. Bhattacharya, N. Sankarayya, 1997, ICCAD 1997.

Modeling and Design Space Exploration for Bit-Cells Based on Voltage-Assisted Switching of Magnetic Tunnel Junctions

Kaushik Roy, Akhilesh Jaiswal, Saima Sharmin, 2016, IEEE Transactions on Electron Devices.

Dual pillar spin torque nano-oscillator

Kaushik Roy, Karthik Yogendra, Mrigank Sharad, 2013 .

Domain-wall shift based multi-level MRAM for high-speed, high-density and energy-efficient caches

Kaushik Roy, Anand Raghunathan, Mrigank Sharad, 2013, 71st Device Research Conference.

Area-Efficient Nonvolatile Flip-Flop Based on Spin Hall Effect

Kaushik Roy, Robert Andrawis, Akhilesh Jaiswal, 2018, IEEE Magnetics Letters.

Magnetic Pattern Recognition Using Injection-Locked Spin-Torque Nano-Oscillators

Kaushik Roy, Karthik Yogendra, Byunghoo Jung, 2016, IEEE Transactions on Electron Devices.

Domino-Style Spin–Orbit Torque-Based Spin Logic

Kaushik Roy, Karthik Yogendra, Yusung Kim, 2015, IEEE Magnetics Letters.

Spin-Orbit-Torque-Based Spin-Dice: A True Random-Number Generator

Kaushik Roy, Xuanyao Fong, Yusung Kim, 2015, IEEE Magnetics Letters.

GaSb-InAs n-TFET With Doped Source Underlap Exhibiting Low Subthreshold Swing at Sub-10-nm Gate-Lengths

Kaushik Roy, K. Roy, Ankit Sharma, 2014, IEEE Electron Device Letters.

Multiple Vth CMOS for Leakage Control in Deep Submicron IC's

Kaushik Roy, Liqiong Wei, 1998 .

TDDB in HfSiON/SiO2 dielectric stack: Büttiker probe based NEGF modeling, prediction and experiment

Kaushik Roy, Yu Cao, Devyani Patra, 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

Device-Circuit Analysis of Double-Gate MOSFETs and Schottky-Barrier FETs: A Comparison Study for Sub-10-nm Technologies

Kaushik Roy, Woo-Suhl Cho, Sumeet Kumar Gupta, 2014, IEEE Transactions on Electron Devices.

Compact models considering incomplete voltage swing in complementary metal oxide semiconductor circuits at ultralow voltages: A circuit perspective on limits of switching energy

Kaushik Roy, Arijit Raychowdhury, Sumeet Kumar Gupta, 2009 .

Spin torques estimation and magnetization dynamics in dual barrier resonant tunneling penta-layer magnetic tunnel junctions

Kaushik Roy, Charles Augustine, Dmitri E. Nikonov, 2010, 68th Device Research Conference.

A Low-Cost Low-Noise Amplifier in Poly-Si TFT Technology

Kaushik Roy, Soo Youn Kim, K. Roy, 2014, Journal of Display Technology.

Sensitivity analysis and optimization of thin-film thermoelectric coolers

Kaushik Roy, Sri Harsha Choday, S. H. Choday, 2013 .

Coupled Spin Torque Nano Oscillators for Low Power Neural Computation

Kaushik Roy, Karthik Yogendra, Deliang Fan, 2015, IEEE Transactions on Magnetics.

Energy recovery circuits using reversible and partially reversible logic

Kaushik Roy, Yibin Ye, 1996 .

Exploring Low Temperature Poly-Si for Low Cost and Low Power Sub-micron Digital Operation

Kaushik Roy, Jing Li, Aditya Bansal, 2006, 2006 64th Device Research Conference.

Cascaded carry-select adder (C2SA): a new structure for low-power CSA design

Yiran Chen, Kaushik Roy, Hai Li, 2005 .

A Physical Model for Grain-Boundary-Induced Threshold Voltage Variation in Polysilicon Thin-Film Transistors

Kaushik Roy, Chih-Hsiang Ho, K. Roy, 2012, IEEE Transactions on Electron Devices.

The effect of process variation on device temperature in FinFET circuits

Kaushik Roy, Jayathi Y. Murthy, Jung Hwan Choi, 2007, ICCAD 2007.