Cheng-Kok Koh

发表

Passivity-preserving model reduction via a computationally efficient project-and-balance scheme

Cheng-Kok Koh, Ngai Wong, Venkataramanan Balakrishnan, 2004, Proceedings. 41st Design Automation Conference, 2004..

Analytical placement of mixed-size circuits for better detailed-routability

Cheng-Kok Koh, Shuai Li, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Session details: Cross-talk noise analysis and management

Cheng-Kok Koh, 2002, DAC '02.

Analytical estimates of stress around a doubly periodic arrangement of through-silicon vias

Cheng-Kok Koh, Ganesh Subbarayan, Anirudh Udupa, 2013, Microelectron. Reliab..

Power supply noise aware floorplanning and decoupling capacitance placement

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Guest editorial: Special section on cross-domain physical optimization

Cheng-Kok Koh, Jiang Hu, 2013, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Routability-driven placement and white space allocation

Jason Cong, Cheng-Kok Koh, Min Xie, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Exploring SOI device structures and interconnect architectures for 3-dimensional integration

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Simultaneous Buffer and Wire Sizing for Performaince and Power

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1996 .

Interconnect layout optimization under higher order RLC model forMCM designs

Jason Cong, Cheng-Kok Koh, Patrick H. Madden, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Statistical based link insertion for robust clock network design

Yiran Chen, Cheng-Kok Koh, Venkataramanan Balakrishnan, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits

Cheng-Kok Koh, Duo Chen, Jongwon Lee, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Construction of reconfigurable clock trees for MCMM designs

Cheng-Kok Koh, Rickard Ewetz, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Non-crossing OBDDs for mapping to regular circuit structures

Cheng-Kok Koh, Aiqun Cao, 2003, Proceedings 21st International Conference on Computer Design.

Construction of Latency-Bounded Clock Trees

Cheng-Kok Koh, Rickard Ewetz, Chuan Yean Tan, 2016, ISPD.

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor

Kaushik Roy, Cheng-Kok Koh, Yiran Chen, 2004 .

A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks

Cheng-Kok Koh, Venkataramanan Balakrishnan, Stephen Cauley, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Interconnect sizing and spacing with consideration of couplingcapacitance

Jason Cong, Cheng-Kok Koh, Lei He, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Postlayout optimization for synthesis of Domino circuits

Cheng-Kok Koh, Chen Li, Aiqun Cao, 2006, TODE.

Bounded-skew clock and Steiner routing under Elmore delay

Jason Cong, Cheng-Kok Koh, Andrew B. Kahng, 1995, ICCAD.

A study on the use of parallel wiring techniques for sub-20nm designs

Cheng-Kok Koh, Ting-Chi Wang, Wen-Hao Liu, 2014, GLSVLSI '14.

Power minimization by simultaneous dual-V/sub th/ assignment and gate-sizing

Cheng-Kok Koh, Kaushik Roy, Liqiong Wei, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

Outreach project introducing computer engineering to high school students

Michael Gasser, Cheng-Kok Koh, Yung-Hsiang Lu, 2010, 2010 IEEE Frontiers in Education Conference (FIE).

Integer linear programming-based synthesis of skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2003, ASP-DAC '03.

Exploring SOI device structures and interconnect architecures for 3-dimensional integration

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001, DAC '01.

Performance optimization of latency insensitive systems through buffer queue sizing of communication channels

Cheng-Kok Koh, Ruibing Lu, Cheng-Kok Koh, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Simultaneous buffer and wire sizing for performance and power optimization

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

Delay-driven layer assignment for advanced technology nodes

Cheng-Kok Koh, Ting-Chi Wang, Wen-Hao Liu, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Simultaneous buffer and wire sizing for performance and power optimization

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

Short-circuit power analysis of an inverter driving an RLC load

Kaushik Roy, Cheng-Kok Koh, Rui Wang, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Construction of reconfigurable clock trees for MCMM designs

Cheng-Kok Koh, Rickard Ewetz, Shankarshana Janarthanan, 2015, DAC.

Processor caches with multi-level spin-transfer torque ram cells

Yiran Chen, Cheng-Kok Koh, Weng-Fai Wong, 2011, ISLPED '11.

SAVS: a self-adaptive variable supply-voltage technique for process-tolerant and power-efficient multi-issue superscalar processor design

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Interconnect design for deep submicron ICs

Jason Cong, Cheng-Kok Koh, Lei He, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation

Cheng-Kok Koh, Ngai Wong, Yuanzhe Wang, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement

Cheng-Kok Koh, Chen Li, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies

Yiran Chen, Cheng-Kok Koh, Weng-Fai Wong, 2009, 2009 IEEE International Conference on Computer Design.

Model reduction in the time-domain using Laguerre polynomials and Krylov methods

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Repeater block planning under simultaneous delay and transition time constraints

Cheng-Kok Koh, Probir Sarkar, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction

Tung-Sang Ng, Cheng-Kok Koh, Ngai Wong, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Tolerating process variations in large, set-associative caches: The buddy cache

Yiran Chen, Cheng-Kok Koh, Weng-Fai Wong, 2009, TACO.

VOSCH: Voltage scaled cache hierarchies

Yiran Chen, Cheng-Kok Koh, Weng-Fai Wong, 2007, 2007 25th International Conference on Computer Design.

A performance and power co-optimization approach for modern processors

Cheng-Kok Koh, Yongxin Zhu, Weng-Fai Wong, 2005, The Fifth International Conference on Computer and Information Technology (CIT'05).

Human-pose estimation with neural-network realization

Cheng-Kok Koh, C. S. George Lee, C. S. G. Lee, 2015, 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS).

Optimal Double Via Insertion With On-Track Preference

Cheng-Kok Koh, Kuang-Yao Lee, Ting-Chi Wang, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

Cheng-Kok Koh, Aiqun Cao, Ruibing Lu, 2003, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Simultaneous driver and wire sizing for performance and power optimization

Jason Cong, Cheng-Kok Koh, 1994, IEEE Trans. Very Large Scale Integr. Syst..

Algorithms and methodologies for routability-driven vlsi placement

Cheng-Kok Koh, Venkataramanan Balakrishnan, Kalliopi Tsota, 2011 .

Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures

Cheng-Kok Koh, Patrick H. Madden, Cheng-Kok Koh, 2000, ACM Great Lakes Symposium on VLSI.

A twisted-bundle layout structure for minimizing inductive coupling noise

Kaushik Roy, Cheng-Kok Koh, Guoan Zhong, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

On-chip interconnect modeling by wire duplication

Kaushik Roy, Cheng-Kok Koh, Guoan Zhong, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Selecting best viewpoint for human-pose estimation

Cheng-Kok Koh, C. S. George Lee, Kai-Chi Chan, 2014, 2014 IEEE International Conference on Robotics and Automation (ICRA).

Parallel Time-Domain Finite-Element Simulator of Linear Speedup and Electromagnetic Accuracy for the Simulation of Die–Package Interaction

Cheng-Kok Koh, Duo Chen, Dan Jiao, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

UST/DME: a clock tree router for general skew constraints

Cheng-Kok Koh, Chung-Wen Albert Tsao, 2000, TODE.

Efficient Analysis of Large-Scale Power Grids Based on a Compact Cholesky Factorization

Cheng-Kok Koh, Hong Li, Venkataramanan Balakrishnan, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

A frequency-domain technique for statistical timing analysis of clock meshes

Cheng-Kok Koh, Ruilin Wang, 2007, ICCAD 2007.

On-chip interconnect modeling by wire duplication

Kaushik Roy, Cheng-Kok Koh, Guoan Zhong, 2002, ICCAD 2002.

Power trends and performance characterization of 3-dimensional integration for future technology generations

Cheng-Kok Koh, Kaushik Roy, Rongtian Zhang, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

A Useful Skew Tree Framework for Inserting Large Safety Margins

Cheng-Kok Koh, Rickard Ewetz, Cheng-Kok Koh, 2015, ISPD.

UST/DME: a clock tree router for general skew constraints

Cheng-Kok Koh, Chung-Wen Albert Tsao, Cheng-Kok Koh, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation

Cheng-Kok Koh, Ngai Wong, Guoyong Shi, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Simultaneous Driver And Wire Sizing For Performance And Power Optimization*

Jason Cong, Cheng-Kok Koh, J. Cong, 1994, IEEE/ACM International Conference on Computer-Aided Design.

MIP-based detailed placer for mixed-size circuits

Cheng-Kok Koh, Shuai Li, 2014, ISPD '14.

A linear-time eigenvalue solver for finite-element-based analysis of large-scale wave propagation problems in on-chip interconnect structures

Cheng-Kok Koh, Jongwon Lee, Dan Jiao, 2008, 2008 IEEE Antennas and Propagation Society International Symposium.

A parallel branch-and-cut approach for detailed placement

Cheng-Kok Koh, Y. Charlie Hu, Venkataramanan Balakrishnan, 2011, TODE.

Scalable Construction of Clock Trees With Useful Skew and High Timing Quality

Cheng-Kok Koh, Rickard Ewetz, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Guest Editorial Special Section on the 2011 International Symposium on Physical Design

Cheng-Kok Koh, Jiang Hu, 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Global interconnect sizing and spacing with consideration of coupling capacitance

Jason Cong, Cheng-Kok Koh, Lei He, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Performance optimization of VLSI interconnect layout

Jason Cong, Cheng-Kok Koh, Lei He, 1996, Integr..

Parallel algorithms for block tridiagonal matrices with applications

Cheng-Kok Koh, Venkataramanan Balakrishnan, Stephen F. Cauley, 2009 .

Performance Analysis and Efficient Implementation of Latency Insensitive Systems

Cheng-Kok Koh, Ruibing Lu, Cheng-Kok Koh, 2003 .

Improving the scalability of SAMBA bus architecture

Cheng-Kok Koh, R. Lu, A. Cao, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Interconnect layout optimization under higher-order RLC model

Jason Cong, Cheng-Kok Koh, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Gated Decap: gate leakage control of on-chip decoupling capacitors in scaled technologies

Yiran Chen, Cheng-Kok Koh, Kaushik Roy, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Global Interconnect Planning

Evangeline F. Y. Young, Cheng-Kok Koh, Yao-Wen Chang, 2008, Handbook of Algorithms for Physical Design Automation.

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Proceedings of the 11th Great Lakes symposium on VLSI

Cheng-Kok Koh, Kaushik Roy, Sung-Mo Kang, 2000 .

On Improving Recursive Bipartitioning-Based Placement

Cheng-Kok Koh, Chen Li, 2003 .

Routability-driven repeater block planning for interconnect-centric floorplanning

Cheng-Kok Koh, Probir Sarkar, Vivek Sundararaman, 2000, ISPD '00.

Mixed block placement via fractional cut recursive bisection

Cheng-Kok Koh, Chen Li, Patrick H. Madden, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies

Cheng-Kok Koh, Hai Li, Kaushik Roy, 2009, IEEE Trans. Very Large Scale Integr. Syst..

Optimization of placement solutions for routability

Cheng-Kok Koh, Yih-Lang Li, Wen-Hao Liu, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Compact and stable modeling of partial inductance and reluctance matrices

Cheng-Kok Koh, Hong Li, Venkataramanan Balakrishnan, 2005, ASP-DAC.

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

Cheng-Kok Koh, Aiqun Cao, Ruibing Lu, 2007, IEEE Trans. Very Large Scale Integr. Syst..

Guiding global placement with wire density

Cheng-Kok Koh, Venkataramanan Balakrishnan, Kalliopi Tsota, 2008, ICCAD 2008.

A metric for analyzing effective on-chip inductive coupling

Kaushik Roy, Cheng-Kok Koh, Guoan Zhong, 2003, ASP-DAC '03.

Post-layout logic duplication for synthesis of Domino circuits with complex gates

Cheng-Kok Koh, Aiqun Cao, Ruibing Lu, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Fast simulation of VLSI interconnects

Cheng-Kok Koh, Venkataramanan Balakrishnan, Jitesh Jain, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Benchmark circuits for clock scheduling and synthesis

Cheng-Kok Koh, Rickard Ewetz, Shankarshana Janarthanan, 2015 .

How to Improve Your Google Ranking: Myths and Reality

Aleksandar Kuzmanovic, Cheng-Kok Koh, Y. Charlie Hu, 2010, 2010 IEEE/WIC/ACM International Conference on Web Intelligence and Intelligent Agent Technology.

Floorplan management: incremental placement for gate sizing and buffer insertion

Cheng-Kok Koh, Chen Li, Patrick H. Madden, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Local merges for effective redundancy in clock networks

Cheng-Kok Koh, Rickard Ewetz, 2013, ISPD '13.

Statistical Timing Analysis Considering Spatial Correlations

Yiran Chen, Cheng-Kok Koh, Hong Li, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Fast clock scheduling and an application to clock tree synthesis

Cheng-Kok Koh, Rickard Ewetz, Cheng-Kok Koh, 2017, Integr..

Synthesis of skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2005, TODE.

Synthesis of clock and power/ground networks

Cheng-Kok Koh, Jitesh Jain, Stephen F. Cauley, 2009 .

Simultaneous driver and wire sizing for performance and power optimization

Jason Cong, Cheng-Kok Koh, 1994, ICCAD.

Minimum-cost bounded-skew clock routing

Jason Cong, Cheng-Kok Koh, J. Cong, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

Synthesis of low power clock trees for handling power-supply variations

Cheng-Kok Koh, Shashank Bujimalla, 2011, ISPD '11.

Processor caches built using multi-level spin-transfer torque RAM cells

Yiran Chen, Cheng-Kok Koh, Hai Li, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Post-layout logic duplication for synthesis of domino circuits with complex gates

Cheng-Kok Koh, Aiqun Cao, Ruibing Lu, 2005, ASP-DAC.

Exact and numerically stable closed-form expressions for potential coefficients of rectangular conductors

Cheng-Kok Koh, Venkataramanan Balakrishnan, Jitesh Jain, 2006, IEEE Trans. Circuits Syst. II Express Briefs.

3D module placement for congestion and power noise reduction

Cheng-Kok Koh, Sung Kyu Lim, Jacob R. Minz, 2005, GLSVLSI '05.

Interconnect planning with local area constrained retiming [logic IC layout]

Cheng-Kok Koh, Ruibing Lu, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Using action classification for human-pose estimation

Cheng-Kok Koh, C. S. George Lee, C. S. G. Lee, 2013, 2013 IEEE/RSJ International Conference on Intelligent Robots and Systems.

SASIMI: sparsity-aware simulation of interconnect-dominated circuits with nonlinear devices

Cheng-Kok Koh, Venkataramanan Balakrishnan, Jitesh Jain, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Decoupling capacitance allocation for power supply noise suppression

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2001, ISPD '01.

Stochastic interconnect modeling, power trends, and performance characterization of 3-D circuits

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001 .

On-chip interconnect modeling by wire duplication

Kaushik Roy, Cheng-Kok Koh, Guoan Zhong, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Rubik: Unlocking the Power of Locality and End-point Flexibility in Cloud Scale Load Balancing

Cheng-Kok Koh, Ming Zhang, Hongqiang Harry Liu, 2015, USENIX Annual Technical Conference.

Skewed CMOS: Noise-immune high-performance low-power static circuit family

Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar, 2000, Proceedings of the 26th European Solid-State Circuits Conference.

Estimation of inductive and resistive switching noise on power supply network in deep sub-micron CMOS circuits

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2000, Proceedings 2000 International Conference on Computer Design.

Optimal post-routing redundant via insertion

Cheng-Kok Koh, Kuang-Yao Lee, Ting-Chi Wang, 2008, ISPD '08.

A direct integral-equation solver of linear complexity for large-scale 3D capacitance and impedance extraction

Cheng-Kok Koh, Dan Jiao, Wenwen Chai, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Exact closed form formula for partial mutual inductances of on-chip interconnects

Cheng-Kok Koh, Guoan Zhong, Cheng-Kok Koh, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Saath: Speeding up CoFlows by Exploiting the Spatial Dimension

Cheng-Kok Koh, Y. Charlie Hu, Rohan Gandhi, 2017, CoNEXT.

Performance Analysis of Arithmetic Operations in Homomorphic Encryption

Cheng-Kok Koh, Yung-Hsiang Lu, Jibang Liu, 2010 .

An Automatic Design of Factors in a Human-Pose Estimation System Using Neural Networks

Cheng-Kok Koh, C. S. George Lee, C. S. G. Lee, 2016, IEEE Transactions on Systems, Man, and Cybernetics: Systems.

Clustering of flip-flops for useful-skew clock tree synthesis

Cheng-Kok Koh, Rickard Ewetz, Chuan Yean Tan, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

Process variation robust clock tree routing

Cheng-Kok Koh, Wai-Ching Douglas Lam, W.-C.D. Lam, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Process variation robust clock tree routing

Cheng-Kok Koh, Wai-Ching Douglas Lam, 2005, ASP-DAC.

Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Cost-Effective Robustness in Clock Networks Using Near-Tree Structures

Cheng-Kok Koh, Rickard Ewetz, Cheng-Kok Koh, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Using The Tetris Game To Teach Computing

Cheng-Kok Koh, Yung-Hsiang Lu, Guangwei Zhu, 2010 .

A study of routability estimation and clustering in placement

Cheng-Kok Koh, Venkataramanan Balakrishnan, Kalliopi Tsota, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Session details: Session 6C: Signal integrity and clock design

Cheng-Kok Koh, Tong Gao, 2001, ICCAD 2001.

A fast Newton/Smith algorithm for solving algebraic Riccati equations and its application in model order reduction

Tung-Sang Ng, Cheng-Kok Koh, Ngai Wong, 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

From O(k2N) to O(N): A fast complex-valued eigenvalue solver for large-scale on-chip interconnect analysis

Cheng-Kok Koh, Jongwon Lee, Dan Jiao, 2009, 2009 IEEE MTT-S International Microwave Symposium Digest.

Collaborative object tracking with motion similarity measure

Cheng-Kok Koh, C. S. George Lee, Kai-Chi Chan, 2013, 2013 IEEE International Conference on Robotics and Biomimetics (ROBIO).

Adaptive admittance-based conductor meshing for interconnect analysis

Cheng-Kok Koh, Venkataramanan Balakrishnan, Ya-Chi Yang, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Finite difference schemes for heat conduction analysis in integrated circuit design and manufacturing

Cheng-Kok Koh, Edmund Y. Lam, Ngai Wong, 2011, Int. J. Circuit Theory Appl..

A two-dimensional domain decomposition technique for the simulation of quantum-scale devices

Cheng-Kok Koh, Venkataramanan Balakrishnan, Gerhard Klimeck, 2012, J. Comput. Phys..

A fast 3-D eigenvalue solver for finite-element-based analysis of multilayered integrated circuits

Cheng-Kok Koh, Jongwon Lee, Dan Jiao, 2010, 2010 IEEE Antennas and Propagation Society International Symposium.

Compact and stable modeling of partial inductance and reluctance matrices

Cheng-Kok Koh, Hong Li, Guoan Zhong, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Frequency domain analysis of switching noise on power supply network

Kaushik Roy, Cheng-Kok Koh, Shiyou Zhao, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Exact and numerically stable closed-form expressions for potential coefficients of rectangular conductors

Cheng-Kok Koh, Venkataramanan Balakrishnan, Jitesh Jain, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

Routability-driven placement and white space allocation

Jason Cong, Cheng-Kok Koh, Min Xie, 2004, ICCAD.

A fast band matching technique for impedance extraction

Cheng-Kok Koh, Hong Li, Venkataramanan Balakrishnan, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Wiresizing with Driver Sizing for Performance and Power Optimization

Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung, 1994 .

Routability-driven repeater block planning for interconnect-centricfloorplanning

Cheng-Kok Koh, Probir Sarkar, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A fast band-matching technique for interconnect inductance modeling

Cheng-Kok Koh, Hong Li, Venkataramanan Balakrishnan, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2001, ISLPED '01.

A factorization-based framework for passivity-preserving model reduction of RLC systems

Cheng-Kok Koh, Venkataramanan Balakrishnan, Q. Su, 2002, DAC '02.

A 3D-point-cloud feature for human-pose estimation

Cheng-Kok Koh, C. S. George Lee, Kai-Chi Chan, 2013, 2013 IEEE International Conference on Robotics and Automation.

Simultaneous redundant via insertion and line end extension for yield optimization

Cheng-Kok Koh, Kuang-Yao Lee, Shing-Tung Lin, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

An Effective Routability-driven Placer for Mixed-size Circuit Designs

Cheng-Kok Koh, Shuai Li, 2013 .

Vlsi interconnect layout optimization

Jason Cong, Cheng-Kok Koh, 1998 .

Clock Tree Construction based on Arrival Time Constraints

Cheng-Kok Koh, Rickard Ewetz, Cheng-Kok Koh, 2017, ISPD.

A high performance bus communication architecture through bus splitting

Cheng-Kok Koh, Ruibing Lu, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Fast clock skew scheduling based on sparse-graph algorithms

Cheng-Kok Koh, Rickard Ewetz, Shankarshana Janarthanan, 2015, The 20th Asia and South Pacific Design Automation Conference.

An adaptive window-based susceptance extraction and its efficient implementation

Kaushik Roy, Cheng-Kok Koh, Venkataramanan Balakrishnan, 2003, DAC '03.

Logic and circuit simulation

Cheng-Kok Koh, Jiun-Lang Huang, Stephen F. Cauley, 2009 .

A size scaling approach for mixed-size placement

Cheng-Kok Koh, Venkataramanan Balakrishnan, Kalliopi Tsota, 2012, ISPD '12.

MCMM clock tree optimization based on slack redistribution using a reduced slack graph

Cheng-Kok Koh, Rickard Ewetz, 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

Flip-flop and repeater insertion for early interconnect planning

Cheng-Kok Koh, Kai-Yuan Chao, Guoan Zhong, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Proceedings of the 2013 ACM international symposium on International symposium on physical design

Cheng-Kok Koh, Cliff C. N. Sze, 2012, ISPD 2013.

Fast simulation of VLSI interconnects

Cheng-Kok Koh, Venkataramanan Balakrishnan, Jitesh Jain, 2004, ICCAD 2004.

Clock scheduling for power supply noise suppression using genetic algorithm with selective gene therapy

Cheng-Kok Koh, Wai-Ching Douglas Lam, Chung-Wen Albert Tsao, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

Yiran Chen, Cheng-Kok Koh, Jing Li, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Routability-driven placement and white space allocation

Jason Cong, Cheng-Kok Koh, Min Xie, 2004, ICCAD 2004.

Stochastic wire-length and delay distributions of 3-dimensional circuits

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

How to Improve Your Search Engine Ranking: Myths and Reality

Aleksandar Kuzmanovic, Cheng-Kok Koh, Y. Charlie Hu, 2014, TWEB.

Mixed integer programming models for detailed placement

Cheng-Kok Koh, Shuai Li, 2012, ISPD '12.

Floorplan management: incremental placement for gate sizing and buffer insertion

Cheng-Kok Koh, Chen Li, P.H. Madden, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Synthesis of selectively clocked skewed logic circuits

Kaushik Roy, Cheng-Kok Koh, Aiqun Cao, 2002, Proceedings International Symposium on Quality Electronic Design.

Recursive bisection based mixed block placement

Cheng-Kok Koh, Chen Li, Patrick H. Madden, 2004, ISPD '04.

Power trends and performance characterization of 3-dimensional integration

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Cascaded carry-select adder (C/sup 2/SA): a new structure for low-power CSA design

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

Exploring SOI device structures and interconnect architectures for low-power high-performance circuits

Cheng-Kok Koh, Rongtian Zhang, D. B. Janes, 2002 .

Fast and Optimal Redundant Via Insertion

Cheng-Kok Koh, Kuang-Yao Lee, Ting-Chi Wang, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Efficient approximate balanced truncation of general large-scale RLC systems via Krylov methods

Cheng-Kok Koh, Venkataramanan Balakrishnan, Q. Su, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Case study for placement solutions in ispd11 and dac12 routability-driven placement contests

Cheng-Kok Koh, Yih-Lang Li, Wen-Hao Liu, 2013, ISPD '13.

Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration

Cheng-Kok Koh, William J. Chappell, Byunghoo Jung, 2006, IEEE Custom Integrated Circuits Conference 2006.

Layout optimization

Jason Cong, Cheng-Kok Koh, Lei He, 1997 .

SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips

Cheng-Kok Koh, Ruibing Lu, 2003, ICCAD.

Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors

Yiran Chen, Kaushik Roy, Cheng-Kok Koh, 2003, ISLPED '03.

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001

Kaushik Roy, Cheng-Kok Koh, Sung-Mo Steve Kang, 2001, ACM Great Lakes Symposium on VLSI.

A frequency-domain technique for statistical timing analysis of clock meshes

Cheng-Kok Koh, Ruilin Wang, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

High-performance low-power carry select adder using dual transition skewed logic

Cheng-Kok Koh, Woopyo Jeong, K. Roy, 2001, Proceedings of the 27th European Solid-State Circuits Conference.

Guiding global placement with wire density

Cheng-Kok Koh, Venkataramanan Balakrishnan, Kalliopi Tsota, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design

Cheng-Kok Koh, Cliff C. N. Sze, 2014, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Post-layout logic optimization of domino circuits

Cheng-Kok Koh, Aiqun Cao, 2004, Proceedings. 41st Design Automation Conference, 2004..

Power supply noise suppression via clock skew scheduling

Cheng-Kok Koh, Wai-Ching Douglas Lam, Chung-Wen Albert Tsao, 2002, Proceedings International Symposium on Quality Electronic Design.

A TSV-cross-link-based approach to 3D-clock network synthesis for improved robustness

Cheng-Kok Koh, Ganesh Subbarayan, Anirudh Udupa, 2014, GLSVLSI '14.

Bounded-skew clock and Steiner routing

Jason Cong, Cheng-Kok Koh, Andrew B. Kahng, 1998, TODE.

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing

Cheng-Kok Koh, Yih-Lang Li, Wen-Hao Liu, 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Interconnect Planning with Local Area Constrained Retiming

Cheng-Kok Koh, Ruibing Lu, 2003 .

Proceedings of the 2017 ACM on International Symposium on Physical Design

Cheng-Kok Koh, Cliff Sze, 2017, ISPD.

Cross link insertion for improving tolerance to variations in clock network synthesis

Cheng-Kok Koh, Tarun Mittal, 2011, ISPD '11.

Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels

Cheng-Kok Koh, Ruibing Lu, 2003, ICCAD 2003.

A high performance bus communication architecture through bus splitting

Cheng-Kok Koh, Ruibing Lu, 2004 .

Performance analysis of latency-insensitive systems

Cheng-Kok Koh, Ruibing Lu, Cheng-Kok Koh, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A 3-D-Point-Cloud System for Human-Pose Estimation

Cheng-Kok Koh, C. S. George Lee, C. S. G. Lee, 2014, IEEE Transactions on Systems, Man, and Cybernetics: Systems.

Session details: Tree construction and buffering

Cheng-Kok Koh, Patrick H. Madden, Cheng-Kok Koh, 2005, ASP-DAC '05.

A Scalable Buffer Queue Sizing Algorithm For Latency Insensitive Systems

Cheng-Kok Koh, Supriyo Maji, 2020 .

Stable and compact inductance modeling of 3-D interconnect structures

Cheng-Kok Koh, Hong Li, Venkataramanan Balakrishnan, 2006, ICCAD.

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

Yiran Chen, Cheng-Kok Koh, Weng-Fai Wong, 2013, JETC.

Improving the scalability of SAMBA bus architecture

Cheng-Kok Koh, Aiqun Cao, Ruibing Lu, 2005, ASP-DAC.

A Scalable, Memory-Efficient Algorithm for Minimum Cycle Mean Calculation in Directed Graphs

Cheng-Kok Koh, Supriyo Maji, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Performance optimization of latency insensitive systems through buffer queue sizing of communication channels

Cheng-Kok Koh, Ruibing Lu, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Non-Crossing Ordered BDD for Physical Synthesis of Regular Circuit Structure

Cheng-Kok Koh, Aiqun Cao, Cheng-Kok Koh, 2003 .

Stochastic Interconnect Modeling , Power Trends , and Performance Characterization of 3-Dimensional Circuits

Kaushik Roy, Cheng-Kok Koh, Rongtian Zhang, 2001 .

A scalable distributed method for quantum-scale device simulation

Cheng-Kok Koh, Venkataramanan Balakrishnan, Stephen F. Cauley, 2007 .

Numerically Stable Algorithms for Inversion of Block Tridiagonal and Banded Matrices

Cheng-Kok Koh, Venkataramanan Balakrishnan, Stephen F. Cauley, 2007 .

From $O(k^{2}N)$ to $O(N)$ : A Fast and High-Capacity Eigenvalue Solver for Full-Wave Extraction of Very Large Scale On-Chip Interconnects

Cheng-Kok Koh, Dan Jiao, V. Balakrishnan, 2009, IEEE Transactions on Microwave Theory and Techniques.

A 3 D-Point-Cloud Feature for Human-Pose Estimation

Cheng-Kok Koh, Kai-Chi Chan, C. S. George Lee, 2013 .

Algorithms for model reduction of large scale rlc systems

Cheng-Kok Koh, Venkataramanan Balakrishnan, Qing Su, 2002 .

A Linear-Time Complex-Valued Eigenvalue Solver for Full-Wave Analysis of Large-Scale On-Chip Interconnect Structures

Cheng-Kok Koh, Dan Jiao, V. Balakrishnan, 2009, IEEE Transactions on Microwave Theory and Techniques.