T. Ritzdorf

Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking

C. Sharbono, T. Ritzdorf, B. Kim, 2006, 56th Electronic Components and Technology Conference 2006.

Formation of TSV for the stacking of advanced logic devices utilizing bumpless wafer-on-wafer technology

Takayuki Ohba, S. W. Kim, Hideki Kitada, 2012 .

Two- and three-dimensional numerical modeling of copper electroplating for advanced ULSI metallization

Gregory J. Wilson, Paul R. McHugh, G. Ritter, 2000 .

A Cu/low-/spl kappa/ dual damascene interconnect for high performance and low cost integrated circuits

Jie Zhou, C. Vo, D. Young, 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).