S. Strangio

Benchmarks of a III–V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders

D. Esseni, S. Strangio, P. Palestri, 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations

S. Strangio, P. Palestri, A. T. Tiedemann, 2018, IEEE Journal of the Electron Devices Society.

Understanding of the intrinsic characteristics and memory trade-offs of sub-μA filamentary RRAM operation

R. Degraeve, L. Goux, A. Fantini, 2013, 2013 Symposium on VLSI Technology.