Minki Cho

发表

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS

Hong Wang, Deepak Mathaikutty, Sriram R. Vangal, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

F max /V min and noise margin impacts of aging on domino read, static write, and retention of 8T 1R1W SRAM arrays in 22nm high-k/metal-gate tri-gate CMOS

Vivek De, Muhammad M. Khellah, James W. Tschanz, 2017, VLSIT 2017.

Signal processing methods and hardware-structure for on-line characterization of thermal gradients in many-core processors

Saibal Mukhopadhyay, Minki Cho, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Perceptual gamut mapping on the basis of image quality and preference factors

Byoung-Ho Kang, Chang-Yeong Kim, Minki Cho, 2006, Electronic Imaging.

Gamut mapping method for ICC saturated intent

Yun-Tae Kim, Minki Cho, Yousun Bang, 2007, Electronic Imaging.

Statistical characterization of radiation-induced pulse waveforms and flip-flop soft errors in 14nm tri-gate CMOS using a back-sampling chain (BSC) technique

James Tschanz, Heather Quinn, Shekhar Borkar, 2017, 2017 Symposium on VLSI Circuits.

Postsilicon Adaptation for Low-Power SRAM under Process Variation

Marilyn Wolf, Jason Schlessman, Hamid Mahmoodi, 2010, IEEE Design & Test of Computers.

Low-power design under variation using error prevention and error tolerance (invited paper)

Kwanyeob Chae, Saibal Mukhopadhyay, Minki Cho, 2012, 2012 13th Latin American Test Workshop (LATW).

Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration

Saibal Mukhopadhyay, Arijit Raychowdhury, Minki Cho, 2010, 2010 IEEE International Test Conference.

Analysis of the impact of interfacial oxide thickness variation on metal-gate high-K circuits

Saibal Mukhopadhyay, Minki Cho, Kingsuk Maitra, 2008, 2008 IEEE Custom Integrated Circuits Conference.

Accuracy-aware SRAM: A reconfigurable low power SRAM architecture for mobile multimedia applications

Jason Schlessman, Wayne H. Wolf, Saibal Mukhopadhyay, 2009, 2009 Asia and South Pacific Design Automation Conference.

Perceptual quality preserving SRAM architecture for color motion pictures

Saibal Mukhopadhyay, Minki Cho, Wen Yueh, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications

Jason Schlessman, Wayne H. Wolf, Saibal Mukhopadhyay, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits

James Tschanz, Chris H. Kim, Shekhar Borkar, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Characterization of Inverse Temperature Dependence in logic circuits

James Tschanz, Kwanyeob Chae, Saibal Mukhopadhyay, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

Design methodology to characterize and compensate for process and temperature variation in digital systems

Minki Cho, 2012 .

FMAX/VMIN and noise margin impacts of aging on domino read, static write, and retention of 8T 1R1W SRAM arrays in 22nm high-k/metal-gate tri-gate CMOS

Muhammad M. Khellah, James W. Tschanz, Carlos Tokunaga, 2017, 2017 Symposium on VLSI Circuits.

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization

Jaydeep Kulkarni, Yuyun Liao, Sriram Vangal, 2019, IEEE Journal of Solid-State Circuits.

Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS

James Tschanz, Vivek De, Muhammad M. Khellah, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Black extraction method using gamut boundary descriptors

Byoung-Ho Kang, Minki Cho, Heui-Keun Choh, 2006, Electronic Imaging.

Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS

James Tschanz, Vivek De, Shekhar Y. Borkar, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating

James Tschanz, Vivek De, Jaydeep P. Kulkarni, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core

James Tschanz, Vivek De, Muhammad M. Khellah, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system

Sung Kyu Lim, Chang Liu, Saibal Mukhopadhyay, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating

James Tschanz, Vivek De, Jaydeep P. Kulkarni, 2017, IEEE Journal of Solid-State Circuits.

A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses

Chris H. Kim, Andres Malavasi, Luke R. Everson, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An All-Digital, $V$ MAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop

James Tschanz, Vivek De, Suyoung Bang, 2019, IEEE Solid-State Circuits Letters.

Energy Introspector : Simulation Infrastructure for Power , Temperature , and Reliability Modeling in Manycore Processors

Sudhakar Yalamanchili, Saibal Mukhopadhyay, William J. Song, 2011 .

Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System

Sung Kyu Lim, Minki Cho, S. Mukhopadhyay, 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.