Harry Sidiropoulos

发表

The VINEYARD Framework for Heterogeneous Cloud Applications: The BrainFrame Case

Christos Strydis, Harry Sidiropoulos, George Chatzikonstantis, 2018, 2018 Conference on Design and Architectures for Signal and Image Processing (DASIP).

From Knights Corner to Landing: A Case Study Based on a Hodgkin-Huxley Neuron Simulator

Esteban Meneses, Christos Strydis, Harry Sidiropoulos, 2017, ISC Workshops.

A novel 3-D FPGA architecture targeting communication intensive applications

Harry Sidiropoulos, Dimitrios Soudris, Kostas Siozios, 2014, J. Syst. Archit..

Multinode implementation of an extended Hodgkin-Huxley simulator

Georgios Smaragdos, Christos Strydis, Harry Sidiropoulos, 2019, Neurocomputing.

On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation

Harry Sidiropoulos, Dimitrios Soudris, Michael Hübner, 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

A novel simulator for extended Hodgkin-Huxley neural networks

Christos Strydis, Harry Sidiropoulos, Dimitrios Soudris, 2020, 2020 IEEE 20th International Conference on Bioinformatics and Bioengineering (BIBE).

A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs

Harry Sidiropoulos, Dimitrios Soudris, Kostas Siozios, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Rapid prototyping of digital controllers using FPGAs and ESL/HLS design methodologies

Harry Sidiropoulos, George Economakos, Christoforos E. Economakos, 2013, 2013 19th International Conference on Automation and Computing.

BrainFrame: a node-level heterogeneous accelerator platform for neuron simulations

Georgios Smaragdos, Christos Strydis, Ioannis Sourdis, 2016, Journal of neural engineering.

A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization

Jürgen Becker, Harry Sidiropoulos, Dimitrios Soudris, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

Efficient C level hardware design for floating point biomedical DSP applications

Harry Sidiropoulos, George Economakos, Christoforos E. Economakos, 2013, 13th IEEE International Conference on BioInformatics and BioEngineering.

Algorithmic and memory optimizations on multiple application mapping onto FPGAs

Harry Sidiropoulos, Dimitrios Soudris, Kostas Siozios, 2017, 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools

Jürgen Becker, Harry Sidiropoulos, Dimitrios Soudris, 2015, ARC.

A Framework for Architecture-Level Exploration of 3-D FPGA Platforms

Harry Sidiropoulos, Dimitrios Soudris, Kostas Siozios, 2011, PATMOS.

On supporting rapid exploration of memory hierarchies onto FPGAs

Harry Sidiropoulos, Dimitrios Soudris, Kostas Siozios, 2013, J. Syst. Archit..

A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs

Harry Sidiropoulos, Dimitrios Soudris, Kostas Siozios, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms

Harry Sidiropoulos, Dimitrios Soudris, Kostas Siozios, 2014, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops.

JITPR: A framework for supporting fast application's implementation onto FPGAs

Jürgen Becker, Harry Sidiropoulos, Dimitrios Soudris, 2013, TRETS.