Ya-Chun Lai

Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)

Shi-Yu Huang, Ya-Chun Lai, 2009, IEEE J. Solid State Circuits.

Resilient Self-V$_{\rm DD}$-Tuning Scheme With Speed-Margining for Low-Power SRAM

Shi-Yu Huang, Hsuan-Jung Hsu, Ya-Chun Lai, 2009, IEEE Journal of Solid-State Circuits.

Resilient SRAM design using BIST-assisted Timing Tracking

Shi-Yu Huang, Ya-Chun Lai, 2007, 2007 IEEE International Workshop on Memory Technology, Design and Testing.

X-Calibration: A Wide-Range Leakage Current Cancellation Technique for Nanometer SRAM Designs

Shi-Yu Huang, Ya-Chun Lai, 2006 .

A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design

Shi-Yu Huang, Ya-Chun Lai, Shi-Yu Huang, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

Shi-Yu Huang, Ya-Chun Lai, Shi-Yu Huang, 2008, IEEE Journal of Solid-State Circuits.