A. Takahashi

发表

Title Yield-aware decomposition for LELE double patterning

Y. Kohira, Yoko Yokoyama, C. Kodama, 2017 .

Optimal Integer Delay-Budget Assignment on

Majid Sarrafzadeh, Atsushi Takahashi, Soheil Ghiasi, 2004 .

Title Yield-aware mask assignment using positive semidefinite relaxation in LELECUT triple patterning

Tomomi Matsui, Satoshi Tanaka, C. Kodama, 2017 .

Chapter 6 Optical Proximity Correction ( OPC ) Under Immersion Lithography

A. Takahashi, Ahmed Awad, 2019 .

A Fast LUT Based Point Intensity Computation for OPC Algorithm*1

Y. Kohira, C. Kodama, A. Takahashi, 2021 .

Mask Manufacturability Aware Post OPC Algorithm For Optical Lithography

A. Takahashi, Ahmed Awad, 2015 .

Single-Layer Trunk Routing Using 45-Degree Lines within Critical Areas for PCB Routing

Y. Kohira, A. Takahashi, K. Shinoda, 2010 .

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling

Atsushi Takahashi, Masahiko Toyonaga, Takuya Yasui, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Fast Clock Scheduling for Peak Power Reduction in LSI

Yasuhiro Takahashi, Y. Kohira, A. Takahashi, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An algorithm to enumerate all floorplans by using Q-sequence and its applications to the boundary constraint problam

Atsushi Takahashi, Liyan Jin, Keishi Sakanushi, 2001 .

An Efficient Algorithm to Extract an Optimal Sub-Circuit by the Minimum Cut

Kengo R. Azegami, Y. Kajitani, A. Takahashi, 2001 .

Air-pressure-model-based fast algorithms for general floorplan

Atsushi Takahashi, Tomonori Izumi, Yoji Kajitani, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

Performance and reliability driven clock scheduling of sequential logic circuits

Atsushi Takahashi, Yoji Kajitani, Y. Kajitani, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Mixed Searching and Proper-Path-Width

Atsushi Takahashi, Yoji Kajitani, Shuichi Ueno, 1991, Theor. Comput. Sci..

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems

Atsushi Takahashi, Yuichi Nakamura, Yasuhiro Takashima, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Integer Solution to a Graph-based Linear Programming Problem

S. Ghiasi, M. Sarrafzadeh, E. Bozorgzadeh, 2003 .

Minimal acyclic forbidden minors for the family of graphs with bounded path-width

Atsushi Takahashi, Yoji Kajitani, Shuichi Ueno, 1994, Discret. Math..

Single-Layer Trunk Routing Using Minimal 45-Degree Lines

Atsushi Takahashi, Yukihide Kohira, Kyosuke Shinoda, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

2-SAT based linear time optimum two-domain clock skew scheduling

Atsushi Takahashi, Yukihide Kohira, Y. Kohira, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

Delay variation tolerant clock scheduling for semi-synchronous circuits

Atsushi Takahashi, H. Matsumura, A. Takahashi, 2001, Asia-Pacific Conference on Circuits and Systems.

Clustering based fast clock scheduling for light clock-tree

Atsushi Takahashi, Makoto Saitoh, Masaaki Azuma, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

A practical clock tree synthesis for semi-synchronous circuits

Atsushi Takahashi, Masahiko Toyonaga, Keiichi Kurokawa, 2000, ISPD '00.

Clock-tree routing realizing a clock-schedule for semi-synchronous circuits

Y. Kajitani, A. Takahashi, Kazunori Inoue, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees

Atsushi Takahashi, Masaaki Azuma, Makoto Saitoh, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Semi-Synchronous Circuit Design Method by Clock Tree Modification ∗ ∗ ∗ ∗

A. Takahashi, S. Ishijima, Tetsuaki Utsumi, 2022 .

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems

Atsushi Takahashi, Yuichi Nakamura, Yasuhiro Takashima, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling

Satoshi Tanaka, Chikaaki Kodama, Atsushi Takahashi, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A fast process variation and pattern fidelity aware mask optimization algorithm

Ahmed Awad, Chikaaki Kodama, Atsushi Takahashi, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Optimal integer delay-budget assignment on directed acyclic graphs

Majid Sarrafzadeh, Atsushi Takahashi, Soheil Ghiasi, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Incremental Timing Budget Management in Programmable Systems

Majid Sarrafzadeh, Atsushi Takahashi, Soheil Ghiasi, 2004, ERSA.

Schedule-clock-tree routing for semi-synchronous circuits

Atsushi Takahashi, Wataru Takahashi, Kazunori Inoue, 1999 .

A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization

Atsushi Takahashi, Yiqiang Sheng, A. Takahashi, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Simulated Annealing Based Approach to Integrated Circuit Layout Design

Yiqiang Sheng, Atsushi Takahashi, A. Takahashi, 2012 .

RRA-based multi-objective optimization to mitigate the worst cases of placement

Atsushi Takahashi, Shuichi Ueno, Yiqiang Sheng, 2011, 2011 9th IEEE International Conference on ASIC.

Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement

Atsushi Takahashi, Shuichi Ueno, Yiqiang Sheng, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Hierarchical BSG floorplan for hierarchical VLSI circuit design

Yoji Kajitani, Atsushi Takahashi, Shigetoshi Nakatake, 2002 .

A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization

Atsushi Takahashi, Yiqiang Sheng, A. Takahashi, 2013, IPSJ Trans. Syst. LSI Des. Methodol..

2-Stage Simulated Annealing with Crossover Operator for 3 D-Packing Volume Minimization

Atsushi Takahashi, Shuichi Ueno, S. Ueno, 2012 .

Clock period minimization of semi-synchronous circuits by gate-level delay insertion

Atsushi Takahashi, Yoji Kajitani, Tomoyuki Yoda, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model

Ahmed Awad, Chikaaki Kodama, Atsushi Takahashi, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A lithographic mask manufacturability and pattern fidelity aware OPC algorithm

Atsushi Takahashi, Ahmed Awad, A. Takahashi, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement

Ahmed Awad, Chikaaki Kodama, Atsushi Takahashi, 2017, IPSJ Trans. Syst. LSI Des. Methodol..