Josep M. Codina

发表

Exploiting pseudo-schedules to guide data dependence graph partitioning

David R. Kaeli, Antonio González, Alex Aletà, 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.

A comparative study of modulo scheduling techniques

Josep Llosa, J. M. Codina, Antonio González, 2002, ICS '02.

Profiling Support for Runtime Managed Code: Next Generation Performance Monitoring Units

Enric Gibert, Josep M. Codina, Raul Martinez, 2015, IEEE Computer Architecture Letters.

Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading

Pedro López, Antonio González, Alejandro Martínez, 2009, 2009 18th International Conference on Parallel Architectures and Compilation Techniques.

A Power-Efficient Co-designed Out-of-Order Processor

J. M. Codina, Antonio González, Josep M. Codina, 2011, 2011 23rd International Symposium on Computer Architecture and High Performance Computing.

Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations

Alejandro Martínez, Fernando Latorre, Josep M. Codina, 2009 .

A unified modulo scheduling and register allocation technique for clustered processors

Antonio González, Josep M. Codina, F. Jesús Sánchez, 2001, Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques.

Boosting single-thread performance in multi-core systems through fine-grain multi-threading

Pedro López, J. M. Codina, Antonio González, 2009, ISCA '09.

A software-hardware hybrid steering mechanism for clustered microarchitectures

José González, Antonio González, Qiong Cai, 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

A HW/SW Co-designed Programmable Functional Unit

J. M. Codina, Antonio González, Josep M. Codina, 2012, IEEE Computer Architecture Letters.

Instruction Replication for Clustered Microarchitectures

David R. Kaeli, Antonio González, Alex Aletà, 2003, MICRO.

Data Prefetching and Targeted Loop Optimizations

Josep Llosa, Antonio Gonzalez, Peter M. W. Knijnenburg, 1999 .

Heterogeneous Clustered VLIW Microarchitectures

David R. Kaeli, Antonio González, Alex Aletà, 2007, International Symposium on Code Generation and Optimization (CGO'07).

The MHAOTEU Toolset

Josep Llosa, Michael F. P. O'Boyle, Olivier Temam, 2000 .

Process for Optimizing an Application

Josep Llosa, Michael F. P. O'Boyle, Olivier Temam, 2000 .

A Co-designed HW/SW Approach to General Purpose Program Acceleration Using a Programmable Functional Unit

J. M. Codina, Antonio González, Josep M. Codina, 2011, 2011 15th Workshop on Interaction between Compilers and Computer Architectures.

Demystifying on-the-fly spill code

David R. Kaeli, J. M. Codina, Antonio González, 2005, PLDI '05.

AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures

David R. Kaeli, J. M. Codina, Antonio González, 2009, IEEE Transactions on Computers.

Virtual Cluster Scheduling Through the Scheduling Graph

J. M. Codina, Antonio González, Josep M. Codina, 2007, International Symposium on Code Generation and Optimization (CGO'07).

Graph-partitioning based instruction scheduling for clustered processors

Antonio González, Alex Aletà, Josep M. Codina, 2001, MICRO.

SoftHV: a HW/SW co-designed processor with horizontal and vertical fusion

J. M. Codina, Antonio González, Josep M. Codina, 2011, CF '11.

Removing communications in clustered microarchitectures through instruction replication

David R. Kaeli, J. M. Codina, Antonio González, 2004, TACO.