Bo-Wei Wu

Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft

Jia-Min Shieh, Chenming Hu, Wen-Cheng Chiu, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

MoS2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS2 availability

Jia-Min Shieh, Yu-Lun Chueh, Chenming Hu, 2016, 2016 IEEE Symposium on VLSI Technology.

A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin

Chenming Hu, ChiaHua Ho, Yi-Ping Hsieh, 2013, 2013 Symposium on VLSI Technology.

Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

Chenming Hu, Yi-Ju Chen, Lain-Jong Li, 2014, 2014 IEEE International Electron Devices Meeting.