M. Kinoshita

1T-1R pillar-type topological-switching random access memory (TRAM) and data retention of GeTe/Sb2Te3 super-lattice films

M. Tai, T. Morikawa, K. Akita, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode

Y. Sasago, T. Mine, S. Hanzawa, 2006, 2009 Symposium on VLSI Technology.

Charge-injection phase change memory with high-quality GeTe/Sb2Te3 superlattice featuring 70-μA RESET, 10-ns SET and 100M endurance cycles operations

T. Yamamoto, M. Tai, K. Kamiya, 2013, 2013 IEEE International Electron Devices Meeting.

Phase-change memory driven by poly-Si MOS transistor with low cost and high-programming gigabyte-per-second throughput

Y. Sasago, T. Mine, M. Tai, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Charge injection Super-lattice Phase Change Memory for low power and high density storage device applications

T. Yamamoto, M. Tai, K. Kamiya, 2013, 2013 Symposium on VLSI Technology.

A low power phase change memory using low thermal conductive doped-Ge2Sb2Te 5 with nano-crystalline structure

M. Tai, T. Morikawa, N. Takaura, 2012, 2012 International Electron Devices Meeting.

Doped In-Ge-Te Phase Change Memory Featuring Stable Operation and Good Data Retention

A. Kotabe, M. Moniwa, S. Hanzawa, 2007, 2007 IEEE International Electron Devices Meeting.

Ta2O5 Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories

M. Moniwa, S. Hanzawa, T. Iwasaki, 2006, 2006 International Electron Devices Meeting.