Jri Lee

International Solid-State Circuits Conference ISSCC 2017 / SESSION 6 / ULTRA-HIGH-SPEED WIRELINE / 6 . 1 6 . 1 A 56 Gb / s PAM-4 / NRZ Transceiver in 40 nm CMOS

Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, 2017 .

A 40-Gb/s Clock and Data Recovery Circuit in

Behzad Razavi, Jri Lee, 2003 .

A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-/spl mu/m CMOS technology

Jian-Yu Ding, Tuan-Yi Cheng, Jri Lee, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

A 7-band 3-8 GHz frequency synthesizer with 1 ns band-switching time in 0.18 /spl mu/m CMOS technology

Jri Lee, Jri Lee, Da-Wei Chiu, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

A 79-GHz bidirectional pulse radar system with injection-regenerative receiver in 65 nm CMOS

Chin-Yang Wu, Pen-Jui Peng, Chiro Kao, 2014, 2014 IEEE Radio Frequency Integrated Circuits Symposium.

11.3 A 7-Band 3-8GHz Frequency Synthesizer

Jri Lee, Da-Wei Chiu, 2005 .

A 60-GHz FSK transceiver with automatically-calibrated demodulator in 90-nm CMOS

Meng-Hsiung Hung, Jri Lee, Huaide Wang, 2010, 2010 Symposium on VLSI Circuits.