Chrysostomos Nicopoulos

发表

TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era

Jongman Kim, Junghee Lee, Chrysostomos Nicopoulos, 2013, TACO.

Analysis and solutions to issue queue process variation

Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, 2008, 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN).

Hardware-Based Job Queue Management for Manycore Architectures and OpenMP Environments

Jongman Kim, Junghee Lee, Chrysostomos Nicopoulos, 2011, 2011 IEEE International Parallel & Distributed Processing Symposium.

ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Network-on-Chip Architectures - A Holistic Design Exploration

Chita R. Das, Narayanan Vijaykrishnan, Chrysostomos Nicopoulos, 2010, Lecture Notes in Electrical Engineering.

CrossOver: Clock domain crossing under virtual-channel flow control

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Anastasios Psarras, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Variation-aware task allocation and scheduling for MPSoC

Narayanan Vijaykrishnan, Xiaoxia Wu, Yuan Xie, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Large-Scale Semantic Concept Detection on Manycore Platforms for Multimedia Mining

Jongman Kim, Chrysostomos Nicopoulos, Mamadou Diao, 2011, 2011 IEEE International Parallel & Distributed Processing Symposium.

ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture

Emmanouil Kalligeros, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, 2014, 2014 Eighth IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling

Junghee Lee, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, 2017, AISTECS@HiPEAC.

Sharded Router: A novel on-chip router architecture employing bandwidth sharding and stealing

Jongman Kim, Junghee Lee, Chrysostomos Nicopoulos, 2013, Parallel Comput..

Do we need wide flits in Networks-on-Chip?

Jongman Kim, Junghee Lee, Chrysostomos Nicopoulos, 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Hardware-Based Online Self-Diagnosis for Faulty Device Identification in Large-Scale IoT Systems

Junghee Lee, Chrysostomos Nicopoulos, Mostafa Hasan, 2018, 2018 IEEE/ACM Third International Conference on Internet-of-Things Design and Implementation (IoTDI).

ElastiStore: An elastic buffer architecture for Network-on-Chip routers

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

The HARPA Approach to Ensure Dependable Performance

Francky Catthoor, Dimitrios Soudris, Chrysostomos Nicopoulos, 2019 .

ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]

Chita R. Das, Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, 2009 .

Size-Aware Cache Management for

Jongman Kim, Junghee Lee, Chrysostomos Nicopoulos, 2015 .

Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Apostolos Stefanidis, 2020, ISPD.

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Yiannakis Sazeides, 2016, ACM Trans. Archit. Code Optim..

Powermax: an automated methodology for generating peak-power traffic in networks-on-chip

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2016, 2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS).

Design and analysis of an NoC architecture from performance, reliability and energy perspective

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2005, 2005 Symposium on Architectures for Networking and Communications Systems (ANCS).

Networks-on-Chip With Double-Data-Rate Links

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Anastasios Psarras, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

Variation-Aware Task and Communication Mapping for MPSoC Architecture

Narayanan Vijaykrishnan, Xiaoxia Wu, Yuan Xie, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Performance and power optimization through data compression in Network-on-Chip architectures

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

An energy- and performance-aware DRAM cache architecture for hybrid DRAM/PCM main memory systems

Jongman Kim, Chrysostomos Nicopoulos, Hyung Gyu Lee, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Monitor and Knob Techniques in Network-on-Chip Architectures

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, William Fornaciari, 2019 .

ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2016, IEEE Transactions on Computers.

DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems

Chrysostomos Nicopoulos, Maria K. Michael, Michael A. Skitsas, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

HARPA: Tackling physically induced performance variability

Francky Catthoor, Dimitrios Soudris, Chrysostomos Nicopoulos, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

A novel dimensionally-decomposed router for on-chip communication in 3D architectures

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2007, ISCA '07.

Evaluating System-Level Monitors and Knobs on Real Hardware

Chrysostomos Nicopoulos, Yiannakis Sazeides, Zacharias Hadjilambrou, 2019 .

Variation-aware task allocation and scheduling for MPSoC

Narayanan Vijaykrishnan, Chrysostomos Nicopoulos, Feng Wang, 2007, ICCAD 2007.

Toward Multi-Layer Holistic Evaluation of System Designs

Chrysostomos Nicopoulos, Yiannakis Sazeides, Emre Özer, 2016, IEEE Computer Architecture Letters.

IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures

Jongman Kim, Sung Kyu Lim, Junghee Lee, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Exploring Fault-Tolerant Network-on-Chip Architectures

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2006, International Conference on Dependable Systems and Networks (DSN'06).

A fine-grained link-level fault-tolerant mechanism for networks-on-chip

Chrysostomos Nicopoulos, Vassos Soteriou, Arseniy Vitkovskiy, 2010, 2010 IEEE International Conference on Computer Design.

A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems

Theocharis Theocharides, Chrysostomos Nicopoulos, Andreas G. Savva, 2017, J. Electr. Comput. Eng..

A programmable processing array architecture supporting dynamic task scheduling and module-level prefetching

Soonhoi Ha, Jongman Kim, Junghee Lee, 2012, CF '12.

A low-power network-on-chip architecture for tile-based chip multi-processors

Junghee Lee, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels

Junghee Lee, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Compression-Based Hybrid MLC/SLC Management Technique for Phase-Change Memory Systems

Jongman Kim, Chrysostomos Nicopoulos, Hyung Gyu Lee, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Low-power dual-edge-triggered synchronous latency-insensitive systems

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Anastasios Psarras, 2018, 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST).

A High-Performance and Energy-Efficient Virtually Tagged Stack Cache Architecture for Multi-core Environments

Jongman Kim, Chrysostomos Nicopoulos, Hyung Gyu Lee, 2011, 2011 IEEE International Conference on High Performance Computing and Communications.

Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Yiannakis Sazeides, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability

Jongman Kim, Chrysostomos Nicopoulos, Vassos Soteriou, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

A highly robust distributed fault-tolerant routing algorithm for NoCs with localized rerouting

Chrysostomos Nicopoulos, Vassos Soteriou, Arseniy Vitkovskiy, 2012, INA-OCMC '12.

Automatic Generation of Peak-Power Traffic for Networks-on-Chip

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]

Chita R. Das, Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, 2009 .

Multi-Armed Bandits for Autonomous Timing-driven Design Optimization

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Apostolos Stefanidis, 2019, 2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS).

DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors

Chrysostomos Nicopoulos, Maria K. Michael, Michael A. Skitsas, 2016, IEEE Transactions on Computers.

Exploration of system availability during software-based self-testing in many-core systems under test latency constraints

Chrysostomos Nicopoulos, Maria K. Michael, Michael A. Skitsas, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

ECM: Effective Capacity Maximizer for high-performance compressed caching

Jongman Kim, Junghee Lee, Chrysostomos Nicopoulos, 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2007 .

Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Dimitrios Mangiras, 2019, 2019 IEEE 4th International Verification and Security Workshop (IVSW).

General-Purpose Computing on Graphics Processing Units (GPGPUs)

Dongkun Shin, Jongman Kim, Junghee Lee, 2017, Encyclopedia of GIS.

Fast Estimations of Failure Probability Over Long Time Spans

Francky Catthoor, Dimitrios Soudris, Chrysostomos Nicopoulos, 2018, 2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs

Chrysostomos Nicopoulos, Maria K. Michael, Michael A. Skitsas, 2018, J. Electron. Test..

ElastiNoC: A Self-Testable Distributed

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2014 .

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects

Chita R. Das, Narayanan Vijaykrishnan, Reetuparna Das, 2007, 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007).

Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression

Jongman Kim, Chrysostomos Nicopoulos, Hyung Gyu Lee, 2014, TODE.

Switch folding: Network-on-Chip routers with time-multiplexed output ports

Emmanouil Kalligeros, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Dual-Clock Multiple-Queue Shared Buffer

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Anastasios Psarras, 2017, IEEE Transactions on Computers.

NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures

Chrysostomos Nicopoulos, Yiannakis Sazeides, Andreas Panteli, 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

Size-Aware Cache Management for Compressed Cache Architectures

Jongman Kim, Junghee Lee, Chrysostomos Nicopoulos, 2015, IEEE Transactions on Computers.

Design and Management of 3D Chip Multiprocessors Using Network-in-Memory

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Yuan Xie, 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

Chrysostomos Nicopoulos, William Fornaciari, Yiannakis Sazeides, 2017, J. Parallel Distributed Comput..

A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs

Chrysostomos Nicopoulos, Vassos Soteriou, Arseniy Vitkovskiy, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Timing-resilient Network-on-Chip architectures

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Anastasios Psarras, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

HoPE: Hot-Cacheline Prediction for Dynamic Early Decompression in Compressed LLCs

Jongman Kim, Jaehyun Park, Junghee Lee, 2017, ACM Trans. Design Autom. Electr. Syst..

A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks

Chita R. Das, Narayanan Vijaykrishnan, Yuan Xie, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Hardware-Assisted Intrusion Detection by Preserving Reference Information Integrity

Jongman Kim, Sang-Won Lee, Junghee Lee, 2013, ICA3PP.

On the Effects of Process Variation in Network-on-Chip Architectures

Chita R. Das, Narayanan Vijaykrishnan, Mary Jane Irwin, 2010, IEEE Transactions on Dependable and Secure Computing.

Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors

Chrysostomos Nicopoulos, Maria K. Michael, Michael A. Skitsas, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures

Jongman Kim, Chrysostomos Nicopoulos, Hyung Gyu Lee, 2012, GLSVLSI '12.

HARPA: Solutions for dependable performance under physically induced performance variability

Francky Catthoor, Dimitrios Soudris, Chrysostomos Nicopoulos, 2015, 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).

Dynamic fault-tolerant routing algorithm for networks-on-chip based on localised detouring paths

Chrysostomos Nicopoulos, Vassos Soteriou, Arseniy Vitkovskiy, 2013, IET Comput. Digit. Tech..

A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects

Chita R. Das, Narayanan Vijaykrishnan, Jongman Kim, 2006, 2006 1st International Conference on Nano-Networks and Workshops.

Subtleties of Run-Time Virtual Address Stacks

Ada Gavrilovska, Jongman Kim, Chrysostomos Nicopoulos, 2015, IEEE Computer Architecture Letters.

Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion

Jongman Kim, Junghee Lee, Chrysostomos Nicopoulos, 2014, Des. Autom. Embed. Syst..

A Probabilistic Model for Soft-Error Rate Estimation in Combinational Logic

Yuan Xie, Chrysostomos Nicopoulos, Emanuele Lattanzi, 2004 .

PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation

Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Ioannis Seitanidis, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).