Luns Tee

9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation

Xiang Li, Li Lin, Fan Zhang, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Recent developments in high integration multi-standard CMOS transceivers for personal communication systems

Li Lin, Jacques C. Rudell, Paul R. Gray, 1998, Proceedings. 1998 International Symposium on Low Power Electronics and Design (IEEE Cat. No.98TH8379).

9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, −246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS

Li Lin, Fan Zhang, Xiang Gao, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers

Li Lin, P.R. Gray, Luns Tee, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

A fully integrated 2×2 MIMO dual-band dual- mode direct-conversion CMOS transceiver for WiMAX/WLAN applications

Li Lin, Ming He, Paul Yu, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Transmitter linearization for portable wireless communication systems

Luns Tee, L. Tee, 2007 .

9.4 A 28nm CMOS digital fractional-N PLL with −245.5dB FOM and a frequency tripler for 802.11abgn/ac radio

Li Lin, Xiang Gao, Wanghua Wu, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.