Kun-Seok Lee

9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation

Xiang Li, Li Lin, Fan Zhang, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A fractional–N frequency synthesizer with a 3–bit 4 th order Σ–Δ modulator

Kun-Seok Lee, Byeong-Ha Park, Min Jong Yoh, 2002 .

A Triple-Mode Balanced Linear CMOS Power Amplifier Using a Switched-Quadrature Coupler

J. Stevenson Kenney, Chang-Ho Lee, Yunseo Park, 2012, IEEE Journal of Solid-State Circuits.

A 2.4-GHz CMOS Power Amplifier With an Integrated Antenna Impedance Mismatch Correction System

Chang-Ho Lee, Youngchang Yoon, Hyungwook Kim, 2014, IEEE Journal of Solid-State Circuits.

A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers

Ockgoo Lee, Songcheol Hong, Dong Ho Lee, 2010, IEEE Journal of Solid-State Circuits.

20.5 A 40nm dual-band 3-stream 802.11a/b/g/n/ac MIMO WLAN SoC with 1.1Gb/s over-the-air throughput

Li Lin, Xiaoyue Wang, Ming He, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

9.4 A 28nm CMOS digital fractional-N PLL with −245.5dB FOM and a frequency tripler for 802.11abgn/ac radio

Li Lin, Xiang Gao, Wanghua Wu, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A Cascode Feedback Bias Technique for Linear CMOS Power Amplifiers in a Multistage Cascode Topology

Ockgoo Lee, J. S. Kenney, Chang-Ho Lee, 2013, IEEE Transactions on Microwave Theory and Techniques.