Y. Yin

Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates

P. Oldiges, B. Haran, H. Bu, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

56nm-pitch low-k/Cu dual-damascene interconnects integration with sidewall image transfer (SIT) patterning scheme

E. Soda, T. Spooner, J. C. Arnold, 2012, 2012 IEEE International Interconnect Technology Conference.

Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

T. Spooner, M. Tagami, M. Colburn, 2011, 2011 IEEE International Interconnect Technology Conference.