J.W. Sleight

Impact of Lateral Asymmetric Channel Doping on 45-nm-Technology N-Type SOI MOSFETs

S. Narasimha, G. Freeman, W. Rausch, 2009, IEEE Transactions on Electron Devices.

A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

G. Biery, S. Narasimha, J. Adkisson, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Integration of Local Stress Techniques with Strained-Si Directly on Insulator (SSDOI) Substrates

Y.H. Kim, M. Ieong, T. Kanarsky, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node

S. Narasimha, N. Zamdmer, J. Bruley, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Stress induced defects and transistor leakage for shallow trench isolated SOI

J. Sleight, G.J. Grula, J.W. Sleight, 1999, IEEE Electron Device Letters.

High-Performance Undoped-Body 8-nm-Thin SOI Field-Effect Transistors

W. Haensch, Zhibin Ren, A. Majumdar, 2008, IEEE Electron Device Letters.

Mainstreaming of the SOI technology

M. Sherony, E. Leobandung, D. Moy, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Aggressively scaled (0.143 /spl mu/m/sup 2/) 6T-SRAM cell for the 32 nm node and beyond

M. Ieong, O. Dokumaci, W. Haensch, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Off-state modulation of SOI floating-body

W. Haensch, J.B. Chang, K. Jenkins, 2006, IEEE Electron Device Letters.

Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths

M. Ieong, Z. Ren, O. Dokumaci, 2005, 2005 IEEE International SOI Conference Proceedings.