Satyajit Anand

发表

A Review on Designing Sub Threshold Flip Flops for Wireless Sensor Network

Partha Pratim Bhattacharya, Neetu Kumari, Nikita Patel, 2019 .

Logical Effort to Study the Performance of 32-bit Heterogeneous Adder

Neha Agarwal, Satyajit Anand, 2013 .

High-Speed Tree-based 64-Bit Binary Comparator using New Approach

Satyajit Anand, Anjuli Anjuli, Satyajit Anand, 2013 .

High-Speed 64-Bit Binary Comparator using Two Stages with Two Different Logic Styles

Satyajit Anand, Anjuli, Satyajit Anand, 2013 .

Automatic Focal Eplileptic Seizure Detection in EEG Signals

Satyajit Anand, Pradeep Kumar Ghosh, Sandeep Jaiswal, 2017, 2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE).

Optimization and Comparison of 4‐Stage Inverter, 2‐i/p NAND Gate, 2‐i/p NOR Gate Driving Standard Load By Using Logical Effort

Satyajit Anand, P. K. Ghosh, 2010 .

A Novel Efficient Machine Learning Approach for Multiclass Classification of EEG Signal

Satyajit Anand, Sandeep Jaiswal, P. K. Ghosh, 2018 .

High-Speed 64-Bit Binary Comparator using Two Different Logic Styles

Satyajit Anand, Anjuli, Satyajit Anand, 2013 .

High-Speed 64-Bit Binary Comparator using Three Stages with CMOS Logic Style

Satyajit Anand, Anjuli Anjuli, Satyajit Anand, 2013 .

A Machine Learning Prediction Model for Automated Brain Abnormalities Detection

Satyajit Anand, Sandeep Jaiswal, P. K. Ghosh, 2018 .

Epileptic Seizure Detection in EEG Signal using Discrete Stationary Wavelet-Based Stockwell Transform

Satyajit Anand, P. K. Ghosh, Sandeep Jaiswal, 2019 .

HIGH-SPEED 64-BIT BINARY COMPARATOR USING NEW APPROACH

Satyajit Anand, Satyajit Anand, 2013 .

Comparative Study of different Flip Flop Cells for WSN Applications

Partha Pratim Bhattacharya, Satyajit Anand, Neetu Kumari, 2014 .

2-Bit Magnitude Comparator Design Using Different Logic Styles

Satyajit Anand, Anjuli, Satyajit Anand, 2013 .

High-performance 64-bit binary comparator

Satyajit Anand, Anjuli, Satyajit Anand, 2014, 2014 International Conference on Reliability Optimization and Information Technology (ICROIT).

A HIGH-SPEED TREE-BASED 64-BIT CMOS BINARY COMPARATOR

Satyajit Anand, Tanner Eda, 2013 .

Design of Low Power Wake-up Receiver for Wireless Sensor Network

Partha Pratim Bhattacharya, Satyajit Anand, Nikita Patel, 2014 .

STUDY AND PERFORMANCE COMPARISON OF VLSI ADDERS USING LOGICAL EFFORT DELAY MODEL

Neha Agarwal, Satyajit Anand, 2012 .

Simulation of a Low Power Wake-Up Receiver for Wireless Sensor Network

Partha Pratim Bhattacharya, Satyajit Anand, Nikita Patel, 2014 .