J.P. Lu

Dual-work-function metal gates by full silicidation of poly-Si with Co-Ni bi-Layers

J. Liu, H.C. Wen, D. Kwong, 2005, IEEE Electron Device Letters.

Damascene integration of copper and ultra-low-k xerogel for high performance interconnects

R. Havemann, J.P. Lu, A.M. Wilson, 1997, International Electron Devices Meeting. IEDM Technical Digest.

A novel nickel SALICIDE process technology for CMOS devices with sub-40 nm physical gate length

J. Zhao, T. Grider, D. Mercer, 2002, Digest. International Electron Devices Meeting,.

Work function tuning of fully silicided NiSi metal gates using a TiN capping layer

H.C. Wen, D. Kwong, H. Wen, 2004, IEEE Electron Device Letters.

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

B. Hornung, C. Machala, A. Krishnan, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

A comparison of TiN processes for CVD W/TiN gate electrode on 3 nm gate oxide

G.A. Brown, J. D. Luttmer, R. Chapman, 1997, International Electron Devices Meeting. IEDM Technical Digest.