K.A. Jenkins

发表

Single pulse output of partially depleted SOI FETs

K.A. Jenkins, Y. Taur, J.Y.-C. Sun, 1996, 1996 IEEE International SOI Conference Proceedings.

Measurement of the effect of self-heating in strained-silicon MOSFETs

K. Jenkins, K. Rim, K.A. Jenkins, 2002, IEEE Electron Device Letters.

A 0.13-/spl mu/m SOI CMOS technology for low-power digital and RF applications

N. Zamdmer, N. Fong, A. Ray, 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).

The importance of distributed grounding in combination with porous Si trenches for the reduction of RF crosstalk through p/sup -/ Si substrate

K.A. Jenkins, Han-Su Kim, Kyuchul Chong, 2003, IEEE Electron Device Letters.

A Faraday cage isolation structure for substrate crosstalk suppression

J. Scholvin, J.A. del Alamo, J.H. Wu, 2001, IEEE Microwave and Wireless Components Letters.

Measurement of I-V curves of silicon-on-insulator (SOI) MOSFET's without self-heating

K.A. Jenkins, J.Y.-C. Sun, 1995, IEEE Electron Device Letters.

High performance sub-40 nm CMOS devices on SOI for the 70 nm technology node

S. Narasimha, N. Zamdmer, J. Bruley, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Novel Bipolar Transistor Isolation Structure Using Combined Selective Epitaxial Growth and Planarization Technique

J.M.C. Stork, R.C. McIntosh, M. Gilbert, 1992, ESSDERC '92: 22nd European Solid State Device Research conference.

A porous Si based novel isolation technology for mixed-signal integrated circuits

Han-Su Kim, Ya-Hong Xie, T. Itoh, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Experimental high performance sub-0.1 /spl mu/m channel nMOSFET's

Y. Taur, T. Lii, D. Quinlan, 1994, IEEE Electron Device Letters.

High-performance emitter-up/down SiGe HBT's

K.A. Jenkins, J.N. Burghartz, C.L. Stanis, 1994, IEEE Electron Device Letters.

Effective crosstalk isolation through p/sup +/ Si substrates with semi-insulating porous Si

K. Jenkins, K.A. Jenkins, Han-Su Kim, 2002, IEEE Electron Device Letters.

Record high RF performance for epitaxial graphene transistors

A. Valdes-Garcia, Y.-M. Lin, Y. Q. Wu, 2011, 2011 International Electron Devices Meeting.

Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

D. Mocuta, S. Narasimha, A. Mocuta, 2002, Digest. International Electron Devices Meeting,.

Partial-SOI isolation structure for reduced bipolar transistor parasitics

J.M.C. Stork, R.C. McIntosh, J. Warnock, 1992, IEEE Electron Device Letters.

On-chip circuit for measuring jitter and skew with picosecond resolution

K.A. Jenkins, K.L. Shepard, A.P. Jose, 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

Opportunities for Standard Silicon Technology in RF&Microwave Applications

M. Soyuer, S. Ponnapalli, K.A. Jenkins, 1995, ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference.

Strained ultrahigh performance fully depleted nMOSFETs with f/sub t/ of 330 GHz and sub-30-nm gate lengths

J. Sleight, M. Ieong, Z. Ren, 2006, IEEE Electron Device Letters.

Frequency response of top-gated carbon nanotube field-effect transistors

D. Neumayer, A. Grill, J. Appenzeller, 2004, IEEE Transactions on Nanotechnology.

Novel in-situ doped polysilicon emitter process with buried diffusion source (BDS)

J.D. Cressler, F. Cardone, K.A. Jenkins, 1991, IEEE Electron Device Letters.

Time-resolved measurements of self-heating in SOI and strained-silicon MOSFETs using photon emission microscopy

S. Polonsky, K. Jenkins, S. Polonsky, 2004, IEEE Electron Device Letters.

SiGe power HBT's for low-voltage, high-performance RF applications

M. Soyuer, K. Jenkins, J. Burghartz, 1998, IEEE Electron Device Letters.

Low-voltage transient bipolar effect induced by dynamic floating-body charging in scaled PD/SOI MOSFETs

S. Krishnan, M.J. Hargrove, J.G. Fossum, 1996, IEEE Electron Device Letters.

Copper-filled through wafer vias with very low inductance

K.A. Jenkins, C.S. Patel, 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications

Liang-Hung Lu, M. Sherony, Jonghae Kim, 2003, IEEE MTT-S International Microwave Symposium Digest, 2003.

A scaled 0.25- mu m bipolar technology using full e-beam lithography

D.D. Tang, E.J. Petrillo, J. Warnock, 1992, IEEE Electron Device Letters.

50-GHz self-aligned silicon bipolar transistors with ion-implanted base profiles

D.D. Tang, T.-C. Chen, J. Warnock, 1990, IEEE Electron Device Letters.

SiGe pMODFETs on silicon-on-sapphire substrates with 116 GHz f/sub max/

I. Lagnado, L. Perraud, R. Hammond, 2001, IEEE Electron Device Letters.

High-performance bipolar technology for improved ECL power delay

D.D. Tang, C. Stanis, J. Warnock, 1991, IEEE Electron Device Letters.

High-performance SiGe pMODFETs grown by UHV-CVD

L. Perraud, R. Hammond, J.O. Chu, 1999, 1999 Symposium on High Performance Electron Devices for Microwave and Optoelectronic Applications. EDMO (Cat. No.99TH8401).