S. Deshpande

A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell

S. Narasimha, A. Gabor, W. Rausch, 2002, Digest. International Electron Devices Meeting,.

Device design considerations for ultra-thin SOI MOSFETs

V. Narayanan, M. Steen, R. Jammy, 2003, IEEE International Electron Devices Meeting 2003.

Lower Resistance Scaled Metal Contacts to Silicide for Advanced CMOS

C. Sheraw, B. Haran, C.-C. Yang, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Reduction of RTA-driven intra-die variation via model-based layout optimization

J.C. Scott, A. Mocuta, B. Goplen, 2006, 2009 Symposium on VLSI Technology.

A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate

R. Booth, C. Radens, V. Sardesai, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.