W. Yan

A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell

S. Narasimha, A. Gabor, W. Rausch, 2002, Digest. International Electron Devices Meeting,.

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

E. Luckowski, H. Bu, V. Narayanan, 2008, 2008 IEEE International Electron Devices Meeting.

A highly cost efficient 8F/sup 2/ DRAM cell with a double gate vertical transistor device for 100 nm and beyond

W. Bergner, W. Mueller, J. Beintner, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).