T. Ono

Advanced scalable ultralow-k/Cu interconnect technology for 32 nm CMOS ULSI using self-assembled porous silica and self-aligned CoWP barrier

K. Kohmura, T. Yoshino, N. Hata, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Proposal of Single Metal/Dual High-$k$ Devices for Aggressively Scaled CMISFETs With Precise Gate Profile Control

Y. Ohji, S. Kamiyama, Y. Nara, 2009, IEEE Transactions on Electron Devices.

Extraction of process-induced damage in low-k/Cu damascene structure

K. Kohmura, T. Yoshino, N. Hata, 2005, ISSM 2005, IEEE International Symposium on Semiconductor Manufacturing, 2005..