H. Ochimizu

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.

Further Enhancement of Electro-migration Resistance by Combination of Self-aligned Barrier and Copper Wiring Encapsulation Techniques for 32-nm Nodes and Beyond

T. Suzuki, T. Sugii, H. Kitada, 2008, 2008 International Interconnect Technology Conference.

Copper Wiring Encapsulation with Ultra-thin Barriers to Enhance Wiring and Dielectric Reliabilities for 32-nm Nodes and Beyond

T. Sugii, H. Kitada, N. Ohtsuka, 2007, 2007 IEEE International Electron Devices Meeting.

The influence of the size effect of copper interconnects on RC delay variability beyond 45nm technology

H. Kitada, T. Nakamura, N. Ohtsuka, 2007, 2007 IEEE International Interconnect Technology Conferencee.