M. Okuno

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.

45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

T. Miyashita, Masaki Yamabe, Tetsu Tanaka, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..